From 7790afb1f303654aacabf81a87f18730c9313061 Mon Sep 17 00:00:00 2001 From: hrydgard Date: Sun, 14 Dec 2008 23:22:56 +0000 Subject: [PATCH] add (disabled) instruction reordering pass to PPCAnalyst. intent is to move cmp instructions towards their conditional branches, and merge them wherever possible. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@1544 8ced0084-cf51-0410-be5f-012b33b47a6e --- Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp | 2 +- .../Core/Src/PowerPC/Jit64/Jit_Integer.cpp | 3 + Source/Core/Core/Src/PowerPC/PPCAnalyst.cpp | 146 ++++++++++--- Source/Core/Core/Src/PowerPC/PPCAnalyst.h | 3 +- Source/Core/Core/Src/PowerPC/PPCTables.cpp | 203 +++++++++--------- Source/Core/Core/Src/PowerPC/PPCTables.h | 10 +- 6 files changed, 232 insertions(+), 135 deletions(-) diff --git a/Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp b/Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp index 8d01a65b04..347feb25b1 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp +++ b/Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp @@ -309,7 +309,7 @@ namespace Jit64 if (emaddress == 0) PanicAlert("ERROR : Trying to compile at 0. LR=%08x", LR); - u32 size; + int size; js.isLastInstruction = false; js.blockStart = emaddress; js.fifoBytesThisBlock = 0; diff --git a/Source/Core/Core/Src/PowerPC/Jit64/Jit_Integer.cpp b/Source/Core/Core/Src/PowerPC/Jit64/Jit_Integer.cpp index fa37c26a32..3ec04f8d6d 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64/Jit_Integer.cpp +++ b/Source/Core/Core/Src/PowerPC/Jit64/Jit_Integer.cpp @@ -136,6 +136,9 @@ namespace Jit64 // unsigned void cmpli(UGeckoInstruction inst) { + // Should check if the next intruction is a branch - if it is, merge the two. This can save + // a whole bunch of instructions and cycles, especially if we aggressively bubble down compares + // towards branches. #ifdef JIT_OFF_OPTIONS if(Core::g_CoreStartupParameter.bJITOff || Core::g_CoreStartupParameter.bJITIntegerOff) {Default(inst); return;} // turn off from debugger diff --git a/Source/Core/Core/Src/PowerPC/PPCAnalyst.cpp b/Source/Core/Core/Src/PowerPC/PPCAnalyst.cpp index 43aad8b6fd..59620b762d 100644 --- a/Source/Core/Core/Src/PowerPC/PPCAnalyst.cpp +++ b/Source/Core/Core/Src/PowerPC/PPCAnalyst.cpp @@ -293,7 +293,60 @@ void ShuffleUp(CodeOp *code, int first, int last) code[last] = temp; } -CodeOp *Flatten(u32 address, u32 &realsize, BlockStats &st, BlockRegStats &gpa, BlockRegStats &fpa) +// IMPORTANT - CURRENTLY ASSUMES THAT A IS A COMPARE +bool CanSwapAdjacentOps(const CodeOp &a, const CodeOp &b) +{ + // Disabled for now + return false; + + const GekkoOPInfo *a_info = GetOpInfo(a.inst); + const GekkoOPInfo *b_info = GetOpInfo(b.inst); + int a_flags = a_info->flags; + int b_flags = b_info->flags; + if (b_flags & (FL_SET_CRx | FL_ENDBLOCK | FL_TIMER | FL_EVIL)) + return false; + if ((b_flags & (FL_RC_BIT | FL_RC_BIT_F)) && (b.inst.hex & 1)) + return false; + + // 10 cmpi, 11 cmpli - we got a compare! + switch (b.inst.OPCD) + { + case 16: + case 18: + //branches. Do not swap. + case 17: //sc + case 46: //lmw + case 19: //table19 - lots of tricky stuff + return false; + } + + // For now, only integer ops acceptable. + switch (b_info->type) { + case OPTYPE_INTEGER: + break; + default: + return false; + } + + // Check that we have no register collisions. + bool no_swap = false; + for (int j = 0; j < 3; j++) + { + int regIn = a.regsIn[j]; + if (regIn < 0) + continue; + if (b.regsOut[0] == regIn || + b.regsOut[1] == regIn) + { + // reg collision! don't swap + return false; + } + } + + return true; +} + +CodeOp *Flatten(u32 address, int &realsize, BlockStats &st, BlockRegStats &gpa, BlockRegStats &fpa) { int numCycles = 0; u32 blockstart = address; @@ -357,7 +410,6 @@ CodeOp *Flatten(u32 address, u32 &realsize, BlockStats &st, BlockRegStats &gpa, code[i].inst = inst; code[i].branchTo = -1; code[i].branchToIndex = -1; - code[i].x86ptr = 0; GekkoOPInfo *opinfo = GetOpInfo(inst); if (opinfo) numCycles += opinfo->numCyclesMinusOne + 1; @@ -427,6 +479,10 @@ CodeOp *Flatten(u32 address, u32 &realsize, BlockStats &st, BlockRegStats &gpa, if (PPCTables::UsesFPU(inst)) fpa.any = true; + code[i].wantsCR0 = false; + code[i].wantsCR1 = false; + code[i].wantsPS1 = false; + const GekkoOPInfo *opinfo = GetOpInfo(code[i].inst); _assert_msg_(GEKKO, opinfo != 0, "Invalid Op - Error scanning %08x op %08x",address+i*4,inst); int flags = opinfo->flags; @@ -462,36 +518,47 @@ CodeOp *Flatten(u32 address, u32 &realsize, BlockStats &st, BlockRegStats &gpa, int numOut = 0; int numIn = 0; + if (flags & FL_OUT_A) + { + code[i].regsOut[numOut++] = inst.RA; + gpa.numWrites[inst.RA]++; + } + if (flags & FL_OUT_D) + { + code[i].regsOut[numOut++] = inst.RD; + gpa.numWrites[inst.RD]++; + } + if (flags & FL_OUT_S) + { + code[i].regsOut[numOut++] = inst.RS; + gpa.numWrites[inst.RS]++; + } + if ((flags & FL_IN_A) || ((flags & FL_IN_A0) && inst.RA != 0)) + { + code[i].regsIn[numIn++] = inst.RA; + gpa.numReads[inst.RA]++; + } + if (flags & FL_IN_B) + { + code[i].regsIn[numIn++] = inst.RB; + gpa.numReads[inst.RB]++; + } + if (flags & FL_IN_C) + { + code[i].regsIn[numIn++] = inst.RC; + gpa.numReads[inst.RC]++; + } + if (flags & FL_IN_S) + { + code[i].regsIn[numIn++] = inst.RS; + gpa.numReads[inst.RS]++; + } + switch (opinfo->type) { case OPTYPE_INTEGER: case OPTYPE_LOAD: case OPTYPE_STORE: - if (flags & FL_OUT_A) - { - code[i].regsOut[numOut++] = inst.RA; - gpa.numWrites[inst.RA]++; - } - if (flags & FL_OUT_D) - { - code[i].regsOut[numOut++] = inst.RD; - gpa.numWrites[inst.RD]++; - } - if ((flags & FL_IN_A) || ((flags & FL_IN_A0) && inst.RA != 0)) - { - code[i].regsIn[numIn++] = inst.RA; - gpa.numReads[inst.RA]++; - } - if (flags & FL_IN_B) - { - code[i].regsIn[numIn++] = inst.RB; - gpa.numReads[inst.RB]++; - } - if (flags & FL_IN_C) - { - code[i].regsIn[numIn++] = inst.RC; - gpa.numReads[inst.RC]++; - } break; case OPTYPE_FPU: break; @@ -523,7 +590,7 @@ CodeOp *Flatten(u32 address, u32 &realsize, BlockStats &st, BlockRegStats &gpa, } for (int j = 0; j < numOut; j++) - { + { int r = code[i].regsOut[j]; if (r < 0 || r > 31) PanicAlert("wtf"); @@ -534,6 +601,29 @@ CodeOp *Flatten(u32 address, u32 &realsize, BlockStats &st, BlockRegStats &gpa, } } + // Instruction Reordering Pass + + // Bubble down compares towards branches, so that they can be merged (merging not yet implemented). + // -2: -1 for the pair, -1 for not swapping with the final instruction which is probably the branch. + for (int i = 0; i < (realsize - 2); i++) + { + CodeOp &a = code[i]; + CodeOp &b = code[i + 1]; + // All integer compares can be reordered. + if ((a.inst.OPCD == 10 || a.inst.OPCD == 11) || + (a.inst.OPCD == 31 && (a.inst.SUBOP10 == 0 || a.inst.SUBOP10 == 32))) + { + // Got a compare instruction. + if (CanSwapAdjacentOps(a, b)) { + // Alright, let's bubble it down! + CodeOp c = a; + a = b; + b = c; + } + } + } + + //Scan for CR0 dependency //assume next block wants CR0 to be safe bool wantsCR0 = true; diff --git a/Source/Core/Core/Src/PowerPC/PPCAnalyst.h b/Source/Core/Core/Src/PowerPC/PPCAnalyst.h index 1508d4740c..3e965d423e 100644 --- a/Source/Core/Core/Src/PowerPC/PPCAnalyst.h +++ b/Source/Core/Core/Src/PowerPC/PPCAnalyst.h @@ -49,7 +49,6 @@ struct CodeOp //16B bool outputCR0; bool outputCR1; bool outputPS1; - const u8 *x86ptr; }; struct BlockStats @@ -82,7 +81,7 @@ void Shutdown(); void ShuffleUp(CodeOp *code, int first, int last); -CodeOp *Flatten(u32 address, u32 &realsize, BlockStats &st, BlockRegStats &gpa, BlockRegStats &fpa); +CodeOp *Flatten(u32 address, int &realsize, BlockStats &st, BlockRegStats &gpa, BlockRegStats &fpa); void LogFunctionCall(u32 addr); diff --git a/Source/Core/Core/Src/PowerPC/PPCTables.cpp b/Source/Core/Core/Src/PowerPC/PPCTables.cpp index 3a7bd2b725..027f593049 100644 --- a/Source/Core/Core/Src/PowerPC/PPCTables.cpp +++ b/Source/Core/Core/Src/PowerPC/PPCTables.cpp @@ -139,59 +139,59 @@ GekkoOPTemplate primarytable[] = {3, Interpreter::twi, Jit64::Default, {"twi", OPTYPE_SYSTEM, 0}}, {17, Interpreter::sc, Jit64::sc, {"sc", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}}, - {7, Interpreter::mulli, Jit64::mulli, {"mulli", OPTYPE_INTEGER, FL_RC_BIT, 2}}, - {8, Interpreter::subfic, Jit64::subfic, {"subfic", OPTYPE_INTEGER, FL_SET_CA}}, - {10, Interpreter::cmpli, Jit64::cmpli, {"cmpli", OPTYPE_INTEGER, FL_SET_CRn}}, - {11, Interpreter::cmpi, Jit64::cmpi, {"cmpi", OPTYPE_INTEGER, FL_SET_CRn}}, - {12, Interpreter::addic, Jit64::reg_imm, {"addic", OPTYPE_INTEGER, FL_SET_CA}}, - {13, Interpreter::addic_rc, Jit64::reg_imm, {"addic_rc", OPTYPE_INTEGER, FL_SET_CR0}}, - {14, Interpreter::addi, Jit64::reg_imm, {"addi", OPTYPE_INTEGER, 0}}, - {15, Interpreter::addis, Jit64::reg_imm, {"addis", OPTYPE_INTEGER, 0}}, + {7, Interpreter::mulli, Jit64::mulli, {"mulli", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_RC_BIT, 2}}, + {8, Interpreter::subfic, Jit64::subfic, {"subfic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}}, + {10, Interpreter::cmpli, Jit64::cmpli, {"cmpli", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}}, + {11, Interpreter::cmpi, Jit64::cmpi, {"cmpi", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}}, + {12, Interpreter::addic, Jit64::reg_imm, {"addic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}}, + {13, Interpreter::addic_rc, Jit64::reg_imm, {"addic_rc", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CR0}}, + {14, Interpreter::addi, Jit64::reg_imm, {"addi", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}}, + {15, Interpreter::addis, Jit64::reg_imm, {"addis", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}}, - {20, Interpreter::rlwimix, Jit64::rlwimix, {"rlwimix", OPTYPE_INTEGER, FL_RC_BIT}}, - {21, Interpreter::rlwinmx, Jit64::rlwinmx, {"rlwinmx", OPTYPE_INTEGER, FL_RC_BIT}}, - {23, Interpreter::rlwnmx, Jit64::rlwnmx, {"rlwnmx", OPTYPE_INTEGER, FL_RC_BIT}}, + {20, Interpreter::rlwimix, Jit64::rlwimix, {"rlwimix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_A | FL_IN_S | FL_RC_BIT}}, + {21, Interpreter::rlwinmx, Jit64::rlwinmx, {"rlwinmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, + {23, Interpreter::rlwnmx, Jit64::rlwnmx, {"rlwnmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_IN_B | FL_RC_BIT}}, - {24, Interpreter::ori, Jit64::reg_imm, {"ori", OPTYPE_INTEGER, 0}}, - {25, Interpreter::oris, Jit64::reg_imm, {"oris", OPTYPE_INTEGER, 0}}, - {26, Interpreter::xori, Jit64::reg_imm, {"xori", OPTYPE_INTEGER, 0}}, - {27, Interpreter::xoris, Jit64::reg_imm, {"xoris", OPTYPE_INTEGER, 0}}, - {28, Interpreter::andi_rc, Jit64::reg_imm, {"andi_rc", OPTYPE_INTEGER, FL_SET_CR0}}, - {29, Interpreter::andis_rc, Jit64::reg_imm, {"andis_rc", OPTYPE_INTEGER, FL_SET_CR0}}, + {24, Interpreter::ori, Jit64::reg_imm, {"ori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, + {25, Interpreter::oris, Jit64::reg_imm, {"oris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, + {26, Interpreter::xori, Jit64::reg_imm, {"xori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, + {27, Interpreter::xoris, Jit64::reg_imm, {"xoris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, + {28, Interpreter::andi_rc, Jit64::reg_imm, {"andi_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}}, + {29, Interpreter::andis_rc, Jit64::reg_imm, {"andis_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}}, - {32, Interpreter::lwz, Jit64::lXz, {"lwz", OPTYPE_LOAD, 0}}, - {33, Interpreter::lwzu, Jit64::Default, {"lwzu", OPTYPE_LOAD, 0}}, - {34, Interpreter::lbz, Jit64::lXz, {"lbz", OPTYPE_LOAD, 0}}, - {35, Interpreter::lbzu, Jit64::Default, {"lbzu", OPTYPE_LOAD, 0}}, - {40, Interpreter::lhz, Jit64::lXz, {"lhz", OPTYPE_LOAD, 0}}, - {41, Interpreter::lhzu, Jit64::Default, {"lhzu", OPTYPE_LOAD, 0}}, - {42, Interpreter::lha, Jit64::lha, {"lha", OPTYPE_LOAD, 0}}, - {43, Interpreter::lhau, Jit64::Default, {"lhau", OPTYPE_LOAD, 0}}, + {32, Interpreter::lwz, Jit64::lXz, {"lwz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, + {33, Interpreter::lwzu, Jit64::Default, {"lwzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, + {34, Interpreter::lbz, Jit64::lXz, {"lbz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, + {35, Interpreter::lbzu, Jit64::Default, {"lbzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, + {40, Interpreter::lhz, Jit64::lXz, {"lhz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, + {41, Interpreter::lhzu, Jit64::Default, {"lhzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, + {42, Interpreter::lha, Jit64::lha, {"lha", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, + {43, Interpreter::lhau, Jit64::Default, {"lhau", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, - {44, Interpreter::sth, Jit64::stX, {"sth", OPTYPE_STORE, 0}}, - {45, Interpreter::sthu, Jit64::stX, {"sthu", OPTYPE_STORE, 0}}, - {36, Interpreter::stw, Jit64::stX, {"stw", OPTYPE_STORE, 0}}, - {37, Interpreter::stwu, Jit64::stX, {"stwu", OPTYPE_STORE, 0}}, - {38, Interpreter::stb, Jit64::stX, {"stb", OPTYPE_STORE, 0}}, - {39, Interpreter::stbu, Jit64::stX, {"stbu", OPTYPE_STORE, 0}}, + {44, Interpreter::sth, Jit64::stX, {"sth", OPTYPE_STORE, FL_IN_A | FL_IN_S}}, + {45, Interpreter::sthu, Jit64::stX, {"sthu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}}, + {36, Interpreter::stw, Jit64::stX, {"stw", OPTYPE_STORE, FL_IN_A | FL_IN_S}}, + {37, Interpreter::stwu, Jit64::stX, {"stwu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}}, + {38, Interpreter::stb, Jit64::stX, {"stb", OPTYPE_STORE, FL_IN_A | FL_IN_S}}, + {39, Interpreter::stbu, Jit64::stX, {"stbu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}}, - {46, Interpreter::lmw, Jit64::lmw, {"lmw", OPTYPE_SYSTEM, 0, 10}}, - {47, Interpreter::stmw, Jit64::stmw, {"stmw", OPTYPE_SYSTEM, 0, 10}}, + {46, Interpreter::lmw, Jit64::lmw, {"lmw", OPTYPE_SYSTEM, FL_EVIL, 10}}, + {47, Interpreter::stmw, Jit64::stmw, {"stmw", OPTYPE_SYSTEM, FL_EVIL, 10}}, - {48, Interpreter::lfs, Jit64::lfs, {"lfs", OPTYPE_LOADFP, 0}}, - {49, Interpreter::lfsu, Jit64::Default, {"lfsu", OPTYPE_LOADFP, 0}}, - {50, Interpreter::lfd, Jit64::lfd, {"lfd", OPTYPE_LOADFP, 0}}, - {51, Interpreter::lfdu, Jit64::Default, {"lfdu", OPTYPE_LOADFP, 0}}, + {48, Interpreter::lfs, Jit64::lfs, {"lfs", OPTYPE_LOADFP, FL_IN_A}}, + {49, Interpreter::lfsu, Jit64::Default, {"lfsu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}}, + {50, Interpreter::lfd, Jit64::lfd, {"lfd", OPTYPE_LOADFP, FL_IN_A}}, + {51, Interpreter::lfdu, Jit64::Default, {"lfdu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}}, - {52, Interpreter::stfs, Jit64::stfs, {"stfs", OPTYPE_STOREFP, 0}}, - {53, Interpreter::stfsu, Jit64::stfs, {"stfsu", OPTYPE_STOREFP, 0}}, - {54, Interpreter::stfd, Jit64::stfd, {"stfd", OPTYPE_STOREFP, 0}}, - {55, Interpreter::stfdu, Jit64::Default, {"stfdu", OPTYPE_STOREFP, 0}}, + {52, Interpreter::stfs, Jit64::stfs, {"stfs", OPTYPE_STOREFP, FL_IN_A}}, + {53, Interpreter::stfsu, Jit64::stfs, {"stfsu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}}, + {54, Interpreter::stfd, Jit64::stfd, {"stfd", OPTYPE_STOREFP, FL_IN_A}}, + {55, Interpreter::stfdu, Jit64::Default, {"stfdu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}}, - {56, Interpreter::psq_l, Jit64::psq_l, {"psq_l", OPTYPE_PS, 0}}, - {57, Interpreter::psq_lu, Jit64::psq_l, {"psq_lu", OPTYPE_PS, 0}}, - {60, Interpreter::psq_st, Jit64::psq_st, {"psq_st", OPTYPE_PS, 0}}, - {61, Interpreter::psq_stu, Jit64::psq_st, {"psq_stu", OPTYPE_PS, 0}}, + {56, Interpreter::psq_l, Jit64::psq_l, {"psq_l", OPTYPE_PS, FL_IN_A}}, + {57, Interpreter::psq_lu, Jit64::psq_l, {"psq_lu", OPTYPE_PS, FL_OUT_A | FL_IN_A}}, + {60, Interpreter::psq_st, Jit64::psq_st, {"psq_st", OPTYPE_PS, FL_IN_A}}, + {61, Interpreter::psq_stu, Jit64::psq_st, {"psq_stu", OPTYPE_PS, FL_OUT_A | FL_IN_A}}, //missing: 0, 5, 6, 9, 22, 30, 62, 58 {0, Interpreter::unknown_instruction, Jit64::Default, {"unknown_instruction", OPTYPE_UNKNOWN, 0}}, @@ -205,7 +205,7 @@ GekkoOPTemplate primarytable[] = }; GekkoOPTemplate table4[] = -{ +{ //SUBOP10 {0, Interpreter::ps_cmpu0, Jit64::Default, {"ps_cmpu0", OPTYPE_PS, FL_SET_CRn}}, {32, Interpreter::ps_cmpo0, Jit64::Default, {"ps_cmpo0", OPTYPE_PS, FL_SET_CRn}}, {40, Interpreter::ps_neg, Jit64::ps_sign, {"ps_neg", OPTYPE_PS, FL_RC_BIT}}, @@ -219,7 +219,7 @@ GekkoOPTemplate table4[] = {592, Interpreter::ps_merge10, Jit64::ps_mergeXX, {"ps_merge10", OPTYPE_PS, FL_RC_BIT}}, {624, Interpreter::ps_merge11, Jit64::ps_mergeXX, {"ps_merge11", OPTYPE_PS, FL_RC_BIT}}, - {1014, Interpreter::dcbz_l, Jit64::Default, {"dcbz_l", OPTYPE_SYSTEM, 0}}, + {1014, Interpreter::dcbz_l, Jit64::Default, {"dcbz_l", OPTYPE_SYSTEM, 0}}, }; GekkoOPTemplate table4_2[] = @@ -243,6 +243,7 @@ GekkoOPTemplate table4_2[] = {31, Interpreter::ps_nmadd, Jit64::ps_maddXX, {"ps_nmadd", OPTYPE_PS, 0}}, }; + GekkoOPTemplate table4_3[] = { {6, Interpreter::psq_lx, Jit64::Default, {"psq_lx", OPTYPE_PS, 0}}, @@ -255,17 +256,17 @@ GekkoOPTemplate table19[] = { {528, Interpreter::bcctrx, Jit64::bcctrx, {"bcctrx", OPTYPE_BRANCH, FL_ENDBLOCK}}, {16, Interpreter::bclrx, Jit64::bclrx, {"bclrx", OPTYPE_BRANCH, FL_ENDBLOCK}}, - {257, Interpreter::crand, Jit64::Default, {"crand", OPTYPE_CR, 0}}, - {129, Interpreter::crandc, Jit64::Default, {"crandc", OPTYPE_CR, 0}}, - {289, Interpreter::creqv, Jit64::Default, {"creqv", OPTYPE_CR, 0}}, - {225, Interpreter::crnand, Jit64::Default, {"crnand", OPTYPE_CR, 0}}, - {33, Interpreter::crnor, Jit64::Default, {"crnor", OPTYPE_CR, 0}}, - {449, Interpreter::cror, Jit64::Default, {"cror", OPTYPE_CR, 0}}, - {417, Interpreter::crorc, Jit64::Default, {"crorc", OPTYPE_CR, 0}}, - {193, Interpreter::crxor, Jit64::Default, {"crxor", OPTYPE_CR, 0}}, + {257, Interpreter::crand, Jit64::Default, {"crand", OPTYPE_CR, FL_EVIL}}, + {129, Interpreter::crandc, Jit64::Default, {"crandc", OPTYPE_CR, FL_EVIL}}, + {289, Interpreter::creqv, Jit64::Default, {"creqv", OPTYPE_CR, FL_EVIL}}, + {225, Interpreter::crnand, Jit64::Default, {"crnand", OPTYPE_CR, FL_EVIL}}, + {33, Interpreter::crnor, Jit64::Default, {"crnor", OPTYPE_CR, FL_EVIL}}, + {449, Interpreter::cror, Jit64::Default, {"cror", OPTYPE_CR, FL_EVIL}}, + {417, Interpreter::crorc, Jit64::Default, {"crorc", OPTYPE_CR, FL_EVIL}}, + {193, Interpreter::crxor, Jit64::Default, {"crxor", OPTYPE_CR, FL_EVIL}}, - {150, Interpreter::isync, Jit64::DoNothing, {"isync", OPTYPE_ICACHE, 0 }}, - {0, Interpreter::mcrf, Jit64::Default, {"mcrf", OPTYPE_SYSTEM, 0}}, + {150, Interpreter::isync, Jit64::DoNothing, {"isync", OPTYPE_ICACHE, FL_EVIL}}, + {0, Interpreter::mcrf, Jit64::Default, {"mcrf", OPTYPE_SYSTEM, FL_EVIL}}, {50, Interpreter::rfi, Jit64::rfi, {"rfi", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS, 1}}, {18, Interpreter::rfid, Jit64::Default, {"rfid", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS}} @@ -274,23 +275,23 @@ GekkoOPTemplate table19[] = GekkoOPTemplate table31[] = { - {28, Interpreter::andx, Jit64::andx, {"andx", OPTYPE_INTEGER, FL_IN_AB | FL_OUT_S | FL_RC_BIT}}, - {60, Interpreter::andcx, Jit64::Default, {"andcx", OPTYPE_INTEGER, FL_IN_AB | FL_OUT_S | FL_RC_BIT}}, - {444, Interpreter::orx, Jit64::orx, {"orx", OPTYPE_INTEGER, FL_IN_AB | FL_OUT_S | FL_RC_BIT}}, - {124, Interpreter::norx, Jit64::Default, {"norx", OPTYPE_INTEGER, FL_IN_AB | FL_OUT_S | FL_RC_BIT}}, - {316, Interpreter::xorx, Jit64::xorx, {"xorx", OPTYPE_INTEGER, FL_IN_AB | FL_OUT_S | FL_RC_BIT}}, - {412, Interpreter::orcx, Jit64::Default, {"orcx", OPTYPE_INTEGER, FL_IN_AB | FL_OUT_S | FL_RC_BIT}}, - {476, Interpreter::nandx, Jit64::Default, {"nandx", OPTYPE_INTEGER, FL_IN_AB | FL_OUT_S | FL_RC_BIT}}, - {284, Interpreter::eqvx, Jit64::Default, {"eqvx", OPTYPE_INTEGER, FL_IN_AB | FL_OUT_S | FL_RC_BIT}}, + {28, Interpreter::andx, Jit64::andx, {"andx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, + {60, Interpreter::andcx, Jit64::Default, {"andcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, + {444, Interpreter::orx, Jit64::orx, {"orx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, + {124, Interpreter::norx, Jit64::Default, {"norx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, + {316, Interpreter::xorx, Jit64::xorx, {"xorx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, + {412, Interpreter::orcx, Jit64::Default, {"orcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, + {476, Interpreter::nandx, Jit64::Default, {"nandx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, + {284, Interpreter::eqvx, Jit64::Default, {"eqvx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {0, Interpreter::cmp, Jit64::cmp, {"cmp", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}}, {32, Interpreter::cmpl, Jit64::cmpl, {"cmpl", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}}, - {26, Interpreter::cntlzwx, Jit64::cntlzwx, {"cntlzwx",OPTYPE_INTEGER, FL_IN_A | FL_OUT_S | FL_RC_BIT}}, - {922, Interpreter::extshx, Jit64::extshx, {"extshx", OPTYPE_INTEGER, FL_IN_A | FL_OUT_S | FL_RC_BIT}}, - {954, Interpreter::extsbx, Jit64::extsbx, {"extsbx", OPTYPE_INTEGER, FL_IN_A | FL_OUT_S | FL_RC_BIT}}, - {536, Interpreter::srwx, Jit64::srwx, {"srwx", OPTYPE_INTEGER, FL_RC_BIT}}, - {792, Interpreter::srawx, Jit64::srawx, {"srawx", OPTYPE_INTEGER, FL_RC_BIT}}, - {824, Interpreter::srawix, Jit64::srawix, {"srawix", OPTYPE_INTEGER, FL_RC_BIT}}, - {24, Interpreter::slwx, Jit64::slwx, {"slwx", OPTYPE_INTEGER, FL_RC_BIT}}, + {26, Interpreter::cntlzwx, Jit64::cntlzwx, {"cntlzwx",OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, + {922, Interpreter::extshx, Jit64::extshx, {"extshx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, + {954, Interpreter::extsbx, Jit64::extsbx, {"extsbx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, + {536, Interpreter::srwx, Jit64::srwx, {"srwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, + {792, Interpreter::srawx, Jit64::srawx, {"srawx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, + {824, Interpreter::srawix, Jit64::srawix, {"srawix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, + {24, Interpreter::slwx, Jit64::slwx, {"slwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {54, Interpreter::dcbst, Jit64::Default, {"dcbst", OPTYPE_DCACHE, 0, 4}}, {86, Interpreter::dcbf, Jit64::Default, {"dcbf", OPTYPE_DCACHE, 0, 4}}, @@ -302,19 +303,19 @@ GekkoOPTemplate table31[] = //load word {23, Interpreter::lwzx, Jit64::lwzx, {"lwzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, - {55, Interpreter::lwzux, Jit64::Default, {"lwzux", OPTYPE_LOAD, FL_OUT_D | FL_IN_A | FL_IN_B}}, + {55, Interpreter::lwzux, Jit64::Default, {"lwzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, //load halfword {279, Interpreter::lhzx, Jit64::Default, {"lhzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, - {311, Interpreter::lhzux, Jit64::Default, {"lhzux", OPTYPE_LOAD, FL_OUT_D | FL_IN_A | FL_IN_B}}, + {311, Interpreter::lhzux, Jit64::Default, {"lhzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, //load halfword signextend {343, Interpreter::lhax, Jit64::lhax, {"lhax", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, - {375, Interpreter::lhaux, Jit64::Default, {"lhaux", OPTYPE_LOAD, FL_OUT_D | FL_IN_A | FL_IN_B}}, + {375, Interpreter::lhaux, Jit64::Default, {"lhaux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, //load byte {87, Interpreter::lbzx, Jit64::lbzx, {"lbzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, - {119, Interpreter::lbzux, Jit64::Default, {"lbzux", OPTYPE_LOAD, FL_OUT_D | FL_IN_A | FL_IN_B}}, + {119, Interpreter::lbzux, Jit64::Default, {"lbzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, //load byte reverse {534, Interpreter::lwbrx, Jit64::Default, {"lwbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, @@ -330,15 +331,15 @@ GekkoOPTemplate table31[] = //store word {151, Interpreter::stwx, Jit64::Default, {"stwx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, - {183, Interpreter::stwux, Jit64::Default, {"stwux", OPTYPE_STORE, FL_IN_A | FL_IN_B}}, + {183, Interpreter::stwux, Jit64::Default, {"stwux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}}, //store halfword {407, Interpreter::sthx, Jit64::Default, {"sthx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, - {439, Interpreter::sthux, Jit64::Default, {"sthux", OPTYPE_STORE, FL_IN_A | FL_IN_B}}, + {439, Interpreter::sthux, Jit64::Default, {"sthux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}}, //store byte {215, Interpreter::stbx, Jit64::Default, {"stbx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, - {247, Interpreter::stbux, Jit64::Default, {"stbux", OPTYPE_STORE, FL_IN_A | FL_IN_B}}, + {247, Interpreter::stbux, Jit64::Default, {"stbux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}}, //store bytereverse {662, Interpreter::stwbrx, Jit64::Default, {"stwbrx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, @@ -359,18 +360,18 @@ GekkoOPTemplate table31[] = {759, Interpreter::stfdux, Jit64::Default, {"stfdux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}}, {983, Interpreter::stfiwx, Jit64::Default, {"stfiwx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}}, - {19, Interpreter::mfcr, Jit64::mfcr, {"mfcr", OPTYPE_SYSTEM, 0}}, - {83, Interpreter::mfmsr, Jit64::mfmsr, {"mfmsr", OPTYPE_SYSTEM, 0}}, + {19, Interpreter::mfcr, Jit64::mfcr, {"mfcr", OPTYPE_SYSTEM, FL_OUT_D}}, + {83, Interpreter::mfmsr, Jit64::mfmsr, {"mfmsr", OPTYPE_SYSTEM, FL_OUT_D}}, {144, Interpreter::mtcrf, Jit64::mtcrf, {"mtcrf", OPTYPE_SYSTEM, 0}}, {146, Interpreter::mtmsr, Jit64::mtmsr, {"mtmsr", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {210, Interpreter::mtsr, Jit64::Default, {"mtsr", OPTYPE_SYSTEM, 0}}, {242, Interpreter::mtsrin, Jit64::Default, {"mtsrin", OPTYPE_SYSTEM, 0}}, - {339, Interpreter::mfspr, Jit64::mfspr, {"mfspr", OPTYPE_SPR, 0}}, + {339, Interpreter::mfspr, Jit64::mfspr, {"mfspr", OPTYPE_SPR, FL_OUT_D}}, {467, Interpreter::mtspr, Jit64::mtspr, {"mtspr", OPTYPE_SPR, 0, 2}}, - {371, Interpreter::mftb, Jit64::mftb, {"mftb", OPTYPE_SYSTEM, FL_TIMER}}, + {371, Interpreter::mftb, Jit64::mftb, {"mftb", OPTYPE_SYSTEM, FL_OUT_D | FL_TIMER}}, {512, Interpreter::mcrxr, Jit64::Default, {"mcrxr", OPTYPE_SYSTEM, 0}}, - {595, Interpreter::mfsr, Jit64::Default, {"mfsr", OPTYPE_SYSTEM, 0, 2}}, - {659, Interpreter::mfsrin, Jit64::Default, {"mfsrin", OPTYPE_SYSTEM, 0, 2}}, + {595, Interpreter::mfsr, Jit64::Default, {"mfsr", OPTYPE_SYSTEM, FL_OUT_D, 2}}, + {659, Interpreter::mfsrin, Jit64::Default, {"mfsrin", OPTYPE_SYSTEM, FL_OUT_D, 2}}, {4, Interpreter::tw, Jit64::Default, {"tw", OPTYPE_SYSTEM, 0, 1}}, {598, Interpreter::sync, Jit64::DoNothing, {"sync", OPTYPE_SYSTEM, 0, 2}}, @@ -387,22 +388,22 @@ GekkoOPTemplate table31[] = GekkoOPTemplate table31_2[] = { - {266, Interpreter::addx, Jit64::addx, {"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT}}, - {10, Interpreter::addcx, Jit64::Default, {"addcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_SET_CA | FL_RC_BIT}}, - {138, Interpreter::addex, Jit64::addex, {"addex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, - {234, Interpreter::addmex, Jit64::Default, {"addmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, - {202, Interpreter::addzex, Jit64::Default, {"addzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, - {491, Interpreter::divwx, Jit64::Default, {"divwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT, 39}}, - {459, Interpreter::divwux, Jit64::divwux, {"divwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT, 39}}, - {75, Interpreter::mulhwx, Jit64::Default, {"mulhwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT, 4}}, - {11, Interpreter::mulhwux, Jit64::mulhwux, {"mulhwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT, 4}}, - {235, Interpreter::mullwx, Jit64::mullwx, {"mullwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT, 4}}, - {104, Interpreter::negx, Jit64::negx, {"negx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT}}, - {40, Interpreter::subfx, Jit64::subfx, {"subfx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT}}, - {8, Interpreter::subfcx, Jit64::subfcx, {"subfcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_SET_CA | FL_RC_BIT}}, - {136, Interpreter::subfex, Jit64::subfex, {"subfex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, - {232, Interpreter::subfmex, Jit64::Default, {"subfmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, - {200, Interpreter::subfzex, Jit64::Default, {"subfzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, + {266, Interpreter::addx, Jit64::addx, {"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, + {10, Interpreter::addcx, Jit64::Default, {"addcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}}, + {138, Interpreter::addex, Jit64::addex, {"addex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, + {234, Interpreter::addmex, Jit64::Default, {"addmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, + {202, Interpreter::addzex, Jit64::Default, {"addzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, + {491, Interpreter::divwx, Jit64::Default, {"divwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, + {459, Interpreter::divwux, Jit64::divwux, {"divwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, + {75, Interpreter::mulhwx, Jit64::Default, {"mulhwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, + {11, Interpreter::mulhwux, Jit64::mulhwux, {"mulhwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, + {235, Interpreter::mullwx, Jit64::mullwx, {"mullwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, + {104, Interpreter::negx, Jit64::negx, {"negx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, + {40, Interpreter::subfx, Jit64::subfx, {"subfx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, + {8, Interpreter::subfcx, Jit64::subfcx, {"subfcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}}, + {136, Interpreter::subfex, Jit64::subfex, {"subfex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, + {232, Interpreter::subfmex, Jit64::Default, {"subfmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, + {200, Interpreter::subfzex, Jit64::Default, {"subfzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, }; GekkoOPTemplate table59[] = diff --git a/Source/Core/Core/Src/PowerPC/PPCTables.h b/Source/Core/Core/Src/PowerPC/PPCTables.h index c097d22594..33bebabb27 100644 --- a/Source/Core/Core/Src/PowerPC/PPCTables.h +++ b/Source/Core/Core/Src/PowerPC/PPCTables.h @@ -26,6 +26,7 @@ enum FL_SET_CR0 = (1<<0), // FL_SET_CR1 = (1<<1), // FL_SET_CRn = (1<<2), // + FL_SET_CRx = FL_SET_CR0 | FL_SET_CR1 | FL_SET_CRn, // FL_SET_CA = (1<<3), // carry FL_READ_CA = (1<<4), // carry FL_RC_BIT = (1<<5), @@ -35,15 +36,18 @@ enum FL_IN_A0 = (1<<9), FL_IN_B = (1<<10), FL_IN_C = (1<<11), + FL_IN_S = (1<<12), FL_IN_AB = FL_IN_A | FL_IN_B, + FL_IN_SB = FL_IN_S | FL_IN_B, FL_IN_A0B = FL_IN_A0 | FL_IN_B, FL_IN_A0BC = FL_IN_A0 | FL_IN_B | FL_IN_C, - FL_OUT_D = (1<<11), + FL_OUT_D = (1<<13), FL_OUT_S = FL_OUT_D, - FL_OUT_A = (1<<12), - FL_OUT_AD = (1<<13), + FL_OUT_A = (1<<14), + FL_OUT_AD = FL_OUT_A | FL_OUT_D, FL_TIMER = (1<<15), FL_CHECKEXCEPTIONS = (1<<16), + FL_EVIL = (1<<17), }; enum