Fix mtsrin/mfsrin instructions. Not likely to change anything since they are only used by MMU code which doesn't work right anyway.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4837 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -221,17 +221,14 @@ void mfmsr(UGeckoInstruction _inst)
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m_GPR[_inst.RD] = MSR;
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}
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// segment register
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// We can probably ignore all this junk
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void mfsr(UGeckoInstruction _inst)
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{
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m_GPR[_inst.RD] = PowerPC::ppcState.sr[_inst.SR];
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}
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// segment register
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void mfsrin(UGeckoInstruction _inst)
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{
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int index = m_GPR[_inst.RB] & 0xF;
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int index = (m_GPR[_inst.RB] >> 28) & 0xF;
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m_GPR[_inst.RD] = PowerPC::ppcState.sr[index];
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}
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@ -241,19 +238,29 @@ void mtmsr(UGeckoInstruction _inst)
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MSR = m_GPR[_inst.RS];
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}
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// segment register
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void mtsr(UGeckoInstruction _inst)
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{
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PowerPC::ppcState.sr[_inst.SR] = m_GPR[_inst.RS];
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// Segment registers. MMU control.
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void SetSR(int index, u32 value) {
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DEBUG_LOG(POWERPC, "%08x: MMU: Segment register %i set to %08x", PowerPC::ppcState.pc, index, value);
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PowerPC::ppcState.sr[index] = value;
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}
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void mtsr(UGeckoInstruction _inst)
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{
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int index = _inst.SR;
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u32 value = m_GPR[_inst.RS];
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SetSR(index, value);
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}
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// segment register
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void mtsrin(UGeckoInstruction _inst)
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{
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int index = m_GPR[_inst.RB] & 0xF;
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PowerPC::ppcState.sr[index] = m_GPR[_inst.RS];
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int index = (m_GPR[_inst.RB] >> 28) & 0xF;
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u32 value = m_GPR[_inst.RS];
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SetSR(index, value);
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}
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void mftb(UGeckoInstruction _inst)
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{
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int iIndex = (_inst.TBR >> 5) | ((_inst.TBR & 0x1F) << 5);
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@ -349,7 +356,7 @@ void mtspr(UGeckoInstruction _inst)
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// PanicAlert("Locked cache enabled!");
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if (HID2.PSE == 0)
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PanicAlert("WARNING: PSE in HID2 isnt set");
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PanicAlert("WARNING: PSE (paired single enable) in HID2 was unset");
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// bool WriteGatherPipeEnable = (bool)HID2.WPE; //TODO?
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// bool LockedCacheEnable = (bool)HID2.LCE;
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@ -416,6 +423,7 @@ void mtspr(UGeckoInstruction _inst)
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}
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break;
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// Page table base etc
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case SPR_SDR:
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Memory::SDRUpdated();
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break;
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