From 7388c6243990dcd46ccd465fbd906ebc077888ff Mon Sep 17 00:00:00 2001 From: Fiora Date: Wed, 8 Oct 2014 20:06:46 -0700 Subject: [PATCH] JIT: use BLR optimization to avoid anding LR with 0xFFFFFFFC Should save roughly one instruction per blr. --- Source/Core/Core/PowerPC/Jit64/JitAsm.cpp | 1 + Source/Core/Core/PowerPC/Jit64/Jit_Branch.cpp | 6 +++++- Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp | 3 ++- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp b/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp index 7adb93d3b1..b2c1b0855c 100644 --- a/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp +++ b/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp @@ -48,6 +48,7 @@ void Jit64AsmRoutineManager::Generate() ABI_PopRegistersAndAdjustStack({}, 0); FixupBranch skipToRealDispatch = J(SConfig::GetInstance().m_LocalCoreStartupParameter.bEnableDebugging); //skip the sync and compare first time dispatcherMispredictedBLR = GetCodePtr(); + AND(32, PPCSTATE(pc), Imm32(0xFFFFFFFC)); #if 0 // debug mispredicts MOV(32, R(ABI_PARAM1), MDisp(RSP, 8)); // guessed_pc diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_Branch.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_Branch.cpp index 2508fe1417..4e615cafdc 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_Branch.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_Branch.cpp @@ -229,7 +229,11 @@ void Jit64::bclrx(UGeckoInstruction inst) #endif MOV(32, R(RSCRATCH), PPCSTATE_LR); - AND(32, R(RSCRATCH), Imm32(0xFFFFFFFC)); + // We don't have to do this because WriteBLRExit handles it for us. Specifically, since we only ever push + // divisible-by-four instruction addresses onto the stack, if the return address matches, we're already + // good. If it doesn't match, the mispredicted-BLR code handles the fixup. + if (!m_enable_blr_optimization) + AND(32, R(RSCRATCH), Imm32(0xFFFFFFFC)); if (inst.LK) MOV(32, PPCSTATE_LR, Imm32(js.compilerPC + 4)); diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp index ae3b74ee3d..5ec9ef15a2 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp @@ -355,7 +355,8 @@ void Jit64::DoMergedBranch() else if ((js.next_inst.OPCD == 19) && (js.next_inst.SUBOP10 == 16)) // bclrx { MOV(32, R(RSCRATCH), M(&LR)); - AND(32, R(RSCRATCH), Imm32(0xFFFFFFFC)); + if (!m_enable_blr_optimization) + AND(32, R(RSCRATCH), Imm32(0xFFFFFFFC)); if (js.next_inst.LK) MOV(32, M(&LR), Imm32(js.next_compilerPC + 4)); WriteBLRExit();