ARAM: rework DMA
Changes include: * Take into account how different size settings interact * Do ARAM DMA transfers in chunks rather than all-at-once
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booto
parent
73c0a4ee81
commit
70299f2505
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@ -24,6 +24,7 @@
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#include "Core/HW/DSP.h"
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#include <algorithm>
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#include <memory>
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#include "AudioCommon/AudioCommon.h"
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@ -119,12 +120,22 @@ union ARAM_Info
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u16 Hex = 0;
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struct
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{
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u16 size : 6;
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u16 base_size : 3;
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u16 expansion_size : 3;
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u16 unk : 1;
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u16 : 9;
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};
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};
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enum
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{
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ARAM_SIZE_02MB = 0b000,
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ARAM_SIZE_04MB = 0b001,
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ARAM_SIZE_08MB = 0b010,
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ARAM_SIZE_16MB = 0b011,
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ARAM_SIZE_32MB = 0b100,
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};
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// STATE_TO_SAVE
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static ARAMInfo s_ARAM;
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static AudioDMA s_audioDMA;
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@ -165,12 +176,19 @@ static void Do_ARAM_DMA();
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static void GenerateDSPInterrupt(u64 DSPIntType, s64 cyclesLate = 0);
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static CoreTiming::EventType* s_et_GenerateDSPInterrupt;
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static CoreTiming::EventType* s_et_CompleteARAM;
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static CoreTiming::EventType* s_et_ContinueARAM;
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static void CompleteARAM(u64 userdata, s64 cyclesLate)
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static void ContinueARAM(u64 userdata, s64 cyclesLate)
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{
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s_dspState.DMAState = 0;
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GenerateDSPInterrupt(INT_ARAM);
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if (s_arDMA.Cnt.count == 0)
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{
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s_dspState.DMAState = 0;
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GenerateDSPInterrupt(INT_ARAM);
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}
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else
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{
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Do_ARAM_DMA();
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}
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}
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DSPEmulator* GetDSPEmulator()
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@ -182,7 +200,7 @@ void Init(bool hle)
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{
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Reinit(hle);
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s_et_GenerateDSPInterrupt = CoreTiming::RegisterEvent("DSPint", GenerateDSPInterrupt);
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s_et_CompleteARAM = CoreTiming::RegisterEvent("ARAMint", CompleteARAM);
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s_et_ContinueARAM = CoreTiming::RegisterEvent("ARAMint", ContinueARAM);
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}
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void Reinit(bool hle)
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@ -472,116 +490,125 @@ void UpdateAudioDMA()
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}
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}
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static void Do_ARAM_DMA()
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/* Depending on the size ARAM is configured as, the mapping to the underlying physical ARAM can
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* change. These mappings have been confirmed on hardware.*/
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static std::optional<u32> ARAM_02MB_to_16MB(u32 address)
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{
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s_dspState.DMAState = 1;
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// ARAM DMA transfer rate has been measured on real hw
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int ticksToTransfer = (s_arDMA.Cnt.count / 32) * 246;
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CoreTiming::ScheduleEvent(ticksToTransfer, s_et_CompleteARAM);
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// Real hardware DMAs in 32byte chunks, but we can get by with 8byte chunks
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if (s_arDMA.Cnt.dir)
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address &= 0x3ffffe0;
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if (address >= 2 * 1024 * 1024)
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{
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// ARAM -> MRAM
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DEBUG_LOG(DSPINTERFACE, "DMA %08x bytes from ARAM %08x to MRAM %08x PC: %08x",
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s_arDMA.Cnt.count, s_arDMA.ARAddr, s_arDMA.MMAddr, PC);
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// Outgoing data from ARAM is mirrored every 64MB (verified on real HW)
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s_arDMA.ARAddr &= 0x3ffffff;
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s_arDMA.MMAddr &= 0x3ffffff;
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if (s_arDMA.ARAddr < s_ARAM.size)
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{
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while (s_arDMA.Cnt.count)
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{
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// These are logically separated in code to show that a memory map has been set up
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// See below in the write section for more information
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if ((s_ARAM_Info.Hex & 0xf) == 3)
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{
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Memory::Write_U64_Swap(*(u64*)&s_ARAM.ptr[s_arDMA.ARAddr & s_ARAM.mask], s_arDMA.MMAddr);
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}
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else if ((s_ARAM_Info.Hex & 0xf) == 4)
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{
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Memory::Write_U64_Swap(*(u64*)&s_ARAM.ptr[s_arDMA.ARAddr & s_ARAM.mask], s_arDMA.MMAddr);
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}
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else
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{
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Memory::Write_U64_Swap(*(u64*)&s_ARAM.ptr[s_arDMA.ARAddr & s_ARAM.mask], s_arDMA.MMAddr);
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}
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s_arDMA.MMAddr += 8;
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s_arDMA.ARAddr += 8;
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s_arDMA.Cnt.count -= 8;
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}
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}
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else
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{
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// Assuming no external ARAM installed; returns zeros on out of bounds reads (verified on real
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// HW)
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while (s_arDMA.Cnt.count)
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{
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Memory::Write_U64(0, s_arDMA.MMAddr);
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s_arDMA.MMAddr += 8;
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s_arDMA.ARAddr += 8;
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s_arDMA.Cnt.count -= 8;
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}
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}
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}
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else
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{
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// MRAM -> ARAM
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DEBUG_LOG(DSPINTERFACE, "DMA %08x bytes from MRAM %08x to ARAM %08x PC: %08x",
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s_arDMA.Cnt.count, s_arDMA.MMAddr, s_arDMA.ARAddr, PC);
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// Incoming data into ARAM is mirrored every 64MB (verified on real HW)
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s_arDMA.ARAddr &= 0x3ffffff;
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s_arDMA.MMAddr &= 0x3ffffff;
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if (s_arDMA.ARAddr < s_ARAM.size)
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{
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while (s_arDMA.Cnt.count)
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{
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if ((s_ARAM_Info.Hex & 0xf) == 3)
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{
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*(u64*)&s_ARAM.ptr[s_arDMA.ARAddr & s_ARAM.mask] =
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Common::swap64(Memory::Read_U64(s_arDMA.MMAddr));
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}
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else if ((s_ARAM_Info.Hex & 0xf) == 4)
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{
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if (s_arDMA.ARAddr < 0x400000)
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{
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*(u64*)&s_ARAM.ptr[(s_arDMA.ARAddr + 0x400000) & s_ARAM.mask] =
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Common::swap64(Memory::Read_U64(s_arDMA.MMAddr));
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}
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*(u64*)&s_ARAM.ptr[s_arDMA.ARAddr & s_ARAM.mask] =
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Common::swap64(Memory::Read_U64(s_arDMA.MMAddr));
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}
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else
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{
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*(u64*)&s_ARAM.ptr[s_arDMA.ARAddr & s_ARAM.mask] =
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Common::swap64(Memory::Read_U64(s_arDMA.MMAddr));
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}
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s_arDMA.MMAddr += 8;
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s_arDMA.ARAddr += 8;
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s_arDMA.Cnt.count -= 8;
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}
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}
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else
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{
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// Assuming no external ARAM installed; writes nothing to ARAM when out of bounds (verified on
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// real HW)
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s_arDMA.MMAddr += s_arDMA.Cnt.count;
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s_arDMA.ARAddr += s_arDMA.Cnt.count;
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s_arDMA.Cnt.count = 0;
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}
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return std::nullopt;
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}
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return ((address & 0xfffffe00) << 1) | (address & 0x1ff);
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}
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static std::optional<u32> ARAM_04MB_to_16MB(u32 address)
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{
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address &= 0x3ffffe0;
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if (address >= 4 * 1024 * 1024)
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{
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return std::nullopt;
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}
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return ((address & 0xfffffe00) << 1) | (address & 0x1ff);
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}
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static std::optional<u32> ARAM_08MB_to_16MB(u32 address)
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{
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address &= 0x3ffffe0;
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if (address >= 8 * 1024 * 1024)
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{
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return std::nullopt;
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}
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return ((address & 0xfffffe00) << 1) | (address & 0x1ff);
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}
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static std::optional<u32> ARAM_16MB_to_16MB(u32 address)
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{
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address &= 0x3ffffe0;
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if (address >= 16 * 1024 * 1024)
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{
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return std::nullopt;
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}
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return address;
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}
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static std::optional<u32> ARAM_32MB_to_16MB(u32 address)
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{
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address &= 0x3ffffe0;
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if (address >= 32 * 1024 * 1024)
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{
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return std::nullopt;
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}
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return (address & 0xff800000) >> 1 | (address & 0x003fffff);
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}
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using ARAM_ADDRESS_CONVERSION_F = std::optional<u32> (*)(u32 address);
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constexpr ARAM_ADDRESS_CONVERSION_F conversion_functions[8] = {
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ARAM_02MB_to_16MB, ARAM_04MB_to_16MB, ARAM_08MB_to_16MB, ARAM_16MB_to_16MB,
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ARAM_32MB_to_16MB, ARAM_32MB_to_16MB, ARAM_32MB_to_16MB, ARAM_32MB_to_16MB,
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};
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enum
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{
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ARAM_DMA_DIR_TO_ARAM = 0,
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ARAM_DMA_DIR_FROM_ARAM = 1,
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};
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/* Size of the smallest unit of transfer to/from ARAM via DMA. */
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constexpr u32 ARAM_LINE_SIZE = 0x20;
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/* Maximum number of lines to transfer at a time via DMA. */
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constexpr u32 ARAM_MAX_TRANSFER_CHUNKING = 0x10;
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/* The number of clock ticks for each line to be transferred. */
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constexpr u32 TICKS_TO_TRANSFER_LINE = 246;
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static void Do_ARAM_DMA()
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{
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constexpr std::array<const char*, 2> aram_transfer_direction = {"to", "from"};
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s_dspState.DMAState = 1;
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// ARAM is mirrored every 64MB (verified on real HW) - done in address conversion func
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// Source/destination/count aligned to 32 bytes - done in MMIO handler
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u32 lines_to_transfer = std::min(s_arDMA.Cnt.count / ARAM_LINE_SIZE, ARAM_MAX_TRANSFER_CHUNKING);
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u32 ticksToTransfer = lines_to_transfer * TICKS_TO_TRANSFER_LINE;
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CoreTiming::ScheduleEvent(ticksToTransfer, s_et_ContinueARAM);
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DEBUG_LOG(DSPINTERFACE, "DMA %08x bytes %s ARAM %08x %s MRAM %08x PC: %08x", s_arDMA.Cnt.count,
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aram_transfer_direction[s_arDMA.Cnt.dir], s_arDMA.ARAddr,
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aram_transfer_direction[1 - s_arDMA.Cnt.dir], s_arDMA.MMAddr, PC);
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const ARAM_ADDRESS_CONVERSION_F convert_address = conversion_functions[s_ARAM_Info.base_size];
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for (u32 n = 0; n < lines_to_transfer; ++n)
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{
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std::optional<u32> physical_aram_addr = convert_address(s_arDMA.ARAddr);
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if (physical_aram_addr)
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{
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const u8* source = &s_ARAM.ptr[*physical_aram_addr];
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u8* dest = Memory::GetPointer(s_arDMA.MMAddr);
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if (s_arDMA.Cnt.dir == ARAM_DMA_DIR_TO_ARAM)
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{
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source = dest;
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dest = &s_ARAM.ptr[*physical_aram_addr];
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}
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std::copy_n(source, ARAM_LINE_SIZE, dest);
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}
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else
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{
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// ARAM returns zeros on out of bounds reads (verified on real HW)
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// ARAM writes nothing on out of bounds writes (verified on real HW)
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if (s_arDMA.Cnt.dir == ARAM_DMA_DIR_FROM_ARAM)
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{
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std::fill_n(Memory::GetPointer(s_arDMA.MMAddr), ARAM_LINE_SIZE, 0);
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}
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}
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s_arDMA.MMAddr += ARAM_LINE_SIZE;
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s_arDMA.ARAddr += ARAM_LINE_SIZE;
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}
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s_arDMA.Cnt.count -= ARAM_LINE_SIZE * lines_to_transfer;
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}
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// (shuffle2) I still don't believe that this hack is actually needed... :(
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// Maybe the Wii Sports ucode is processed incorrectly?
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// (LM) It just means that DSP reads via '0xffdd' on Wii can end up in EXRAM or main RAM
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u8 ReadARAM(u32 address)
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{
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if (s_ARAM.wii_mode)
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