Fix Gecko codehandler lag.
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TryTwo
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98b0efb6de
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701b5c4b03
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@ -43,6 +43,8 @@ cheatdata:
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.long frozenvalue
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.space 39*4
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# Warning, _strip_and_align expects cheat codes to start on 0x0 or 0x8.
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# Properly compiling it will add a nop if needed.
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_start:
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stwu r1,-172(r1) # stores sp
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stw r0,8(r1) # stores r0
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@ -150,7 +152,7 @@ _readcodes:
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andis. r11,r3,0x1000 #test pointer
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rlwinm r3,r3,0,7,31 #r3 = extract address in r3 (code type 0/1/2) #0x01FFFFFF
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bne +12 #jump lf the pointer is used
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rlwinm r12,r6,0,0,6 #lf pointer is not used, address = base address
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@ -178,6 +180,33 @@ _readcodes:
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b _terminator_onoff_ #code type 7 : End of code list
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_Write_32:
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lwz r18, 0(r12) #Load data from registry that will be written to
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cmpw r18, r5 #Is data to be written equal to the data in memory
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beq+ +72 #Skip if yes
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stw r5, 0(r12) #store opcode
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li r9, 0 #safe, check r9 if more write_32's are linked.
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b +48
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_Write_08x:
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lbzx r18, r9, r12
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rlwinm r0, r4, 0, 24,31 #Clears any other data with r4's byte, for compare
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cmpw r0, r18
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beq+ +44
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stbx r4,r9,r12
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b +24
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_Write_16x:
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lhzx r18, r9, r12
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rlwinm r0, r4, 0, 16,31 #Makes sure r4 is just a halfword for compare
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cmpw r0, r18
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beq+ +20
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sthx r4,r9,r12
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icbi r9, r12 #branch target. Clears cache. Need dcbf?
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sync
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isync
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blr
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#CT0=============================================================================
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#write 8bits (0): 00XXXXXX YYYY00ZZ
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#write 16bits (1): 02XXXXXX YYYYZZZZ
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@ -201,45 +230,34 @@ _write:
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rlwinm r10,r4,16,16,31 #r10 = extract number of times to write (16bits value)
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_write816:
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beq cr4,+32 #lf r5 = 1 then 16 bits write
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stbx r4,r9,r12 #write byte
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add r21, r9, r12
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icbi r0, r21
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sync
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isync
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beq cr4,+16 #lf r5 = 1 then 16 bits write
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bl _Write_08x
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addi r9,r9,1
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b +28
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sthx r4,r9,r12 #write halfword
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add r21, r9, r12 #Get Real Memory Offset
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icbi r0, r21 #Invalidate Icache around real memory offset
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sync
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isync
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addi r9,r9,2
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b +12
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bl _Write_16x
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addi r9, r9, 2
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subic. r10,r10,1 #number of times to write -1
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bge- _write816
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b _readcodes
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_write32:
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rlwinm r12,r12,0,0,29 #32bits align adress
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stw r4,0(r12) #write word to address
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icbi r0, r12 #Invalidate icache around address
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sync
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isync
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mr r5, r4
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bl _Write_32
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b _readcodes
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_write_string: #endianess ?
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mr r9,r4
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mr r22, r4
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bne- cr7,_skip_and_align #lf code execution is false, skip string code data
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_stb:
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subic. r9,r9,1 #r9 -= 1 (and compares r9 with 0)
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blt- _skip_and_align #lf r9 < 0 then exit
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lbzx r5,r9,r15
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stbx r5,r9,r12 #loop until all the data has been written
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add r21, r9, r12 #Get Real Memory Offset
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icbi r0, r21 #Invalidate Icache around real memory offset
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sync
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isync
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mr r4, r5
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bl _Write_08x #loop until all the data has been written
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mr r4, r22
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b _stb
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_write_serial:
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@ -259,15 +277,17 @@ _loop_serial:
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beq- cr5,+16 #lf 16bits
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bgt+ cr5,+20 #lf 32bits
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stbx r4,r9,r12 #write serial byte (CT04,T=0)
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b +16
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sthx r4,r9,r12 #write serial halfword (CT04,T=1)
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b +8
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bl _Write_08x
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b +40
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bl _Write_16x #write serial halfword (CT04,T=1)
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b +32
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lwzx r18, r9, r12
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cmpw r4, r18
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beq+ +20
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stwx r4,r9,r12 #write serial word (CT04,T>=2)
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add r21, r9, r12 #Get Real Memory Offset
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icbi r0, r21 #Invalidate Icache around real memory offset
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icbi r9, r12 #Invalidate Icache around real memory offset
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sync
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isync
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add r4,r4,r11 #value +=VVVVVVVV
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@ -560,35 +580,36 @@ _load:
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bgt+ cr6,+24
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beq- cr6,+12
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lbz r4,0(r4) #load byte at address
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lbz r4,0(r12) #load byte at address
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b _store_reg
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lhz r4,0(r4) #load halfword at address
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lhz r4,0(r12) #load halfword at address
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b _store_reg
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lwz r4,0(r4) #load word at address
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lwz r4,0(r12) #load word at address
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b _store_reg
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_store:
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rlwinm r19,r3,28,20,31 #r9=r3 ror 12 (N84UYZZZ)
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mr r12, r4
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mr r4, r9
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mr r5, r9
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li r9, 0
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_storeloop:
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bgt+ cr6,+32
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beq- cr6,+16
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stb r9,0(r4) #store byte at address
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addi r4,r4,1
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bl _Write_08x #store byte at address
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addi r12,r12,1
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b _storeloopend
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sth r9,0(r4) #store byte at address
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addi r4,r4,2
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bl _Write_16x #store byte at address
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addi r12,r12,2
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b _storeloopend
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stw r9,0(r4) #store byte at address
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icbi r0, r4 #Invalidate at offset given by storing gecko register
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sync
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isync
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addi r4,r4,4
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bl _Write_32
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addi r12,r12,4
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_storeloopend:
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subic. r19,r19,1
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bge _storeloop
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@ -793,14 +814,14 @@ _compare16_counter:
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b _conditional
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#===============================================================================
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#execute (0) : C0000000 NNNNNNNN = execute
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#hook1 (2) : C4XXXXXX NNNNNNNN = insert instructions at XXXXXX
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#execute (0) : C0000000 NNNNNNNN = execute. End with 4E800020 00000000.
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#hook1 (2) : C4XXXXXX NNNNNNNN = insert instructions at XXXXXX. Same as C2.
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#hook2 (3) : C6XXXXXX YYYYYYYY = branch from XXXXXX to YYYYYY
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#on/off (6) : CC000000 00000000 = on/off switch
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#range check (7) : CE000000 XXXXYYYY = is ba/po in XXXX0000-YYYY0000
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_hook_execute:
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mr r26,r4 #r18 = 0YYYYYYY
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mr r26,r4 #r26 = 0YYYYYYY
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rlwinm r4,r4,3,0,28 #r4 = NNNNNNNN*8 = number of lines (and not number of bytes)
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bne- cr4,_hook_addresscheck #lf sub code type != 0
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bne- cr7,_skip_and_align
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@ -815,7 +836,6 @@ _skip_and_align:
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rlwinm r15,r15,0,0,28 #align 64-bit
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b _readcodes
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_hook_addresscheck:
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cmpwi cr4,r5,3
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@ -834,10 +854,7 @@ _hook2:
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sub r4,r4,r12 #r4 = to-from
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rlwimi r5,r4,0,6,29 #r5 = (r4 AND 0x03FFFFFC) OR 0x48000000
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rlwimi r5,r3,0,31,31 #restore lr bit
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stw r5,0(r12) #store opcode
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icbi r0, r12 #Invalidate at branch
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sync
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isync
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bl _Write_32
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b _readcodes
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_hook1:
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@ -845,19 +862,14 @@ _hook1:
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sub r9,r15,r12 #r9 = to-from
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rlwimi r5,r9,0,6,29 #r5 = (r9 AND 0x03FFFFFC) OR 0x48000000
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stw r5,0(r12) #stores b at the hook place (over original instruction)
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icbi r0, r12 #Invalidate at hook location
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sync
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isync
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bl _Write_32
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addi r12,r12,4
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add r11,r15,r4
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subi r11,r11,4 #r11 = address of the last word of the hook1 code
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sub r9,r12,r11
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rlwimi r5,r9,0,6,29 #r5 = (r9 AND 0x03FFFFFC) OR 0x48000000
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stw r5,0(r11) #stores b at the last word of the hook1 code
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icbi r0, r12 #Invalidate at last instruction of hook
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sync
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isync
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mr r12, r11
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bl _Write_32
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b _skip_and_align
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_addresscheck1:
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@ -1045,4 +1057,4 @@ regbuffer:
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codelist:
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.space 2*4
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.end
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.end
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