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JitArm64: Use WZR for ppcState STP optimization with imm == 0

This commit is contained in:
JosJuice 2024-10-21 21:48:44 +02:00
parent 383cbffdec
commit 6fb3e9226b
1 changed files with 10 additions and 6 deletions
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16
Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp
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@ -256,21 +256,25 @@ void Arm64GPRCache::FlushRegisters(BitSet32 regs, FlushMode mode, ARM64Reg tmp_r
OpArg& reg2 = m_guest_registers[GUEST_GPR_OFFSET + i + 1]; OpArg& reg2 = m_guest_registers[GUEST_GPR_OFFSET + i + 1];
const bool reg1_imm = reg1.GetType() == RegType::Immediate; const bool reg1_imm = reg1.GetType() == RegType::Immediate;
const bool reg2_imm = reg2.GetType() == RegType::Immediate; const bool reg2_imm = reg2.GetType() == RegType::Immediate;
const bool reg1_zero = reg1_imm && reg1.GetImm() == 0;
const bool reg2_zero = reg2_imm && reg2.GetImm() == 0;
const bool flush_all = mode == FlushMode::All; const bool flush_all = mode == FlushMode::All;
if (reg1.IsDirty() && reg2.IsDirty() && if (reg1.IsDirty() && reg2.IsDirty() &&
(reg1.GetType() == RegType::Register || (reg1_imm && flush_all)) && (reg1.GetType() == RegType::Register || (reg1_imm && (reg1_zero || flush_all))) &&
(reg2.GetType() == RegType::Register || (reg2_imm && flush_all))) (reg2.GetType() == RegType::Register || (reg2_imm && (reg2_zero || flush_all))))
{ {
const size_t ppc_offset = GetGuestByIndex(i).ppc_offset; const size_t ppc_offset = GetGuestByIndex(i).ppc_offset;
if (ppc_offset <= 252) if (ppc_offset <= 252)
{ {
ARM64Reg RX1 = R(GetGuestByIndex(i)); ARM64Reg RX1 = reg1_zero ? ARM64Reg::WZR : R(GetGuestByIndex(i));
ARM64Reg RX2 = R(GetGuestByIndex(i + 1)); ARM64Reg RX2 = reg2_zero ? ARM64Reg::WZR : R(GetGuestByIndex(i + 1));
m_emit->STP(IndexType::Signed, RX1, RX2, PPC_REG, u32(ppc_offset)); m_emit->STP(IndexType::Signed, RX1, RX2, PPC_REG, u32(ppc_offset));
if (flush_all) if (flush_all)
{ {
UnlockRegister(EncodeRegTo32(RX1)); if (!reg1_zero)
UnlockRegister(EncodeRegTo32(RX2)); UnlockRegister(EncodeRegTo32(RX1));
if (!reg2_zero)
UnlockRegister(EncodeRegTo32(RX2));
reg1.Flush(); reg1.Flush();
reg2.Flush(); reg2.Flush();
} }