ShuriZma
/
dolphin
mirror of https://github.com/dolphin-emu/dolphin.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #6773 from lioncash/fpscr 

PowerPC: Make the PowerPCState's fpscr member variable a UReg_FPSCR instance
This commit is contained in:
Markus Wick 2018-05-07 08:47:14 +02:00 committed by GitHub
parent fcc5095d8c 69a0aaebd4
commit 6ec1e742ae
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
7 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Source/Core/Core/PowerPC/Gekko.h
View File

@ -475,7 +475,7 @@ union UReg_FPSCR
u32 Hex = 0; u32 Hex = 0;
UReg_FPSCR() = default; UReg_FPSCR() = default;
UReg_FPSCR(u32 hex_) : Hex{hex_} {} explicit UReg_FPSCR(u32 hex_) : Hex{hex_} {}
}; };
// Hardware Implementation-Dependent Register 0 // Hardware Implementation-Dependent Register 0

4
Source/Core/Core/PowerPC/Interpreter/Interpreter.cpp
View File

@ -95,8 +95,8 @@ static void Trace(UGeckoInstruction& inst)
DEBUG_LOG(POWERPC, DEBUG_LOG(POWERPC,
"INTER PC: %08x SRR0: %08x SRR1: %08x CRval: %016lx FPSCR: %08x MSR: %08x LR: " "INTER PC: %08x SRR0: %08x SRR1: %08x CRval: %016lx FPSCR: %08x MSR: %08x LR: "
"%08x %s %08x %s", "%08x %s %08x %s",
PC, SRR0, SRR1, (unsigned long)PowerPC::ppcState.cr_val[0], PowerPC::ppcState.fpscr, PC, SRR0, SRR1, (unsigned long)PowerPC::ppcState.cr_val[0], FPSCR.Hex, MSR.Hex,
MSR.Hex, PowerPC::ppcState.spr[8], regs.c_str(), inst.hex, ppc_inst.c_str()); PowerPC::ppcState.spr[8], regs.c_str(), inst.hex, ppc_inst.c_str());
} }
int Interpreter::SingleStepInner() int Interpreter::SingleStepInner()

4
Source/Core/Core/PowerPC/Jit64/Jit.cpp
View File

@ -565,8 +565,8 @@ void Jit64::Trace()
#endif #endif
DEBUG_LOG(DYNA_REC, "JIT64 PC: %08x SRR0: %08x SRR1: %08x FPSCR: %08x MSR: %08x LR: %08x %s %s", DEBUG_LOG(DYNA_REC, "JIT64 PC: %08x SRR0: %08x SRR1: %08x FPSCR: %08x MSR: %08x LR: %08x %s %s",
PC, SRR0, SRR1, PowerPC::ppcState.fpscr, MSR.Hex, PowerPC::ppcState.spr[8], PC, SRR0, SRR1, FPSCR.Hex, MSR.Hex, PowerPC::ppcState.spr[8], regs.c_str(),
regs.c_str(), fregs.c_str()); fregs.c_str());
} }
void Jit64::Jit(u32 em_address) void Jit64::Jit(u32 em_address)

2
Source/Core/Core/PowerPC/PowerPC.cpp
View File

@ -128,7 +128,7 @@ static void ResetRegisters()
ppcState.spr[SPR_ECID_M] = 0x1840c00d; ppcState.spr[SPR_ECID_M] = 0x1840c00d;
ppcState.spr[SPR_ECID_L] = 0x82bb08e8; ppcState.spr[SPR_ECID_L] = 0x82bb08e8;
ppcState.fpscr = 0; ppcState.fpscr.Hex = 0;
ppcState.pc = 0; ppcState.pc = 0;
ppcState.npc = 0; ppcState.npc = 0;
ppcState.Exceptions = 0; ppcState.Exceptions = 0;

6
Source/Core/Core/PowerPC/PowerPC.h
View File

@ -75,8 +75,8 @@ struct PowerPCState
// be manipulated bit by bit fairly easily. // be manipulated bit by bit fairly easily.
u64 cr_val[8]; u64 cr_val[8];
UReg_MSR msr; // machine state register UReg_MSR msr; // machine state register
u32 fpscr; // floating point flags/status bits UReg_FPSCR fpscr; // floating point flags/status bits
// Exception management. // Exception management.
u32 Exceptions; u32 Exceptions;
@ -185,7 +185,7 @@ void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst);
#define MMCR1 ((UReg_MMCR1&)PowerPC::ppcState.spr[SPR_MMCR1]) #define MMCR1 ((UReg_MMCR1&)PowerPC::ppcState.spr[SPR_MMCR1])
#define PC PowerPC::ppcState.pc #define PC PowerPC::ppcState.pc
#define NPC PowerPC::ppcState.npc #define NPC PowerPC::ppcState.npc
#define FPSCR ((UReg_FPSCR&)PowerPC::ppcState.fpscr) #define FPSCR PowerPC::ppcState.fpscr
#define MSR PowerPC::ppcState.msr #define MSR PowerPC::ppcState.msr
#define GPR(n) PowerPC::ppcState.gpr[n] #define GPR(n) PowerPC::ppcState.gpr[n]

4
Source/Core/DolphinQt2/Debugger/RegisterWidget.cpp
View File

@ -292,8 +292,8 @@ void RegisterWidget::PopulateTable()
[](u64 value) { PowerPC::SetXER(UReg_XER(value)); }); [](u64 value) { PowerPC::SetXER(UReg_XER(value)); });
// FPSCR // FPSCR
AddRegister(22, 5, RegisterType::fpscr, "FPSCR", [] { return PowerPC::ppcState.fpscr; }, AddRegister(22, 5, RegisterType::fpscr, "FPSCR", [] { return PowerPC::ppcState.fpscr.Hex; },
[](u64 value) { PowerPC::ppcState.fpscr = value; }); [](u64 value) { PowerPC::ppcState.fpscr.Hex = value; });
// MSR // MSR
AddRegister(23, 5, RegisterType::msr, "MSR", [] { return PowerPC::ppcState.msr.Hex; }, AddRegister(23, 5, RegisterType::msr, "MSR", [] { return PowerPC::ppcState.msr.Hex; },

4
Source/Core/DolphinWX/Debugger/RegisterView.cpp
View File

@ -80,7 +80,7 @@ u32 GetSpecialRegValue(int reg)
case 4: case 4:
return PowerPC::GetXER().Hex; return PowerPC::GetXER().Hex;
case 5: case 5:
return PowerPC::ppcState.fpscr; return PowerPC::ppcState.fpscr.Hex;
case 6: case 6:
return PowerPC::ppcState.msr.Hex; return PowerPC::ppcState.msr.Hex;
case 7: case 7:
@ -124,7 +124,7 @@ void SetSpecialRegValue(int reg, u32 value)
PowerPC::SetXER(UReg_XER(value)); PowerPC::SetXER(UReg_XER(value));
break; break;
case 5: case 5:
PowerPC::ppcState.fpscr = value; PowerPC::ppcState.fpscr.Hex = value;
break; break;
case 6: case 6:
PowerPC::ppcState.msr.Hex = value; PowerPC::ppcState.msr.Hex = value;