From df08a778120185680e3393f23a508f92b6297018 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sat, 10 Nov 2018 10:57:15 +0000 Subject: [PATCH] Jit_LoadStore: Ra needs to be ReadWrite when writeback is required This was an erronous change in 534db3b, Ra was previously loaded but was changed to not being loaded. Why is loading necessary? Loading is necessary because when a memory exception occurs, the current register values are flushed. This occurs before a new value is loaded into Ra, so the previous value is required in Ra. --- Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp index 0c6bb929a2..3bab9436dd 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp @@ -244,7 +244,7 @@ void Jit64::lXXx(UGeckoInstruction inst) } } - RCX64Reg Ra = (update && storeAddress) ? gpr.Bind(a, RCMode::Write) : RCX64Reg{}; + RCX64Reg Ra = (update && storeAddress) ? gpr.Bind(a, RCMode::ReadWrite) : RCX64Reg{}; RegCache::Realize(opAddress, Ra, Rd); BitSet32 registersInUse = CallerSavedRegistersInUse();