Merge in latest changes to ArmEmitter from the PPSSPP crew. Should fix the dumb random crashes I had from IOS icache clearing not initializing a value.
This commit is contained in:
Ryan Houdek
parent
2c722bb04f
commit
6d9c0c8863
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@ -83,6 +83,40 @@ bool TryMakeOperand2_AllowNegation(s32 imm, Operand2 &op2, bool *negated)
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}
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}
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Operand2 AssumeMakeOperand2(u32 imm) {
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Operand2 op2;
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bool result = TryMakeOperand2(imm, op2);
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_dbg_assert_msg_(JIT, result, "Could not make assumed Operand2.");
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return op2;
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}
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bool ARMXEmitter::TrySetValue_TwoOp(ARMReg reg, u32 val)
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{
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int ops = 0;
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for (int i = 0; i < 16; i++)
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{
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if ((val >> (i*2)) & 0x3)
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{
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ops++;
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i+=3;
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}
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}
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if (ops > 2)
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return false;
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bool first = true;
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for (int i = 0; i < 16; i++, val >>=2) {
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if (val & 0x3) {
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first ? MOV(reg, Operand2((u8)val, (u8)((16-i) & 0xF)))
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: ORR(reg, reg, Operand2((u8)val, (u8)((16-i) & 0xF)));
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first = false;
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i+=3;
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val >>= 6;
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}
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}
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return true;
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}
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void ARMXEmitter::MOVI2F(ARMReg dest, float val, ARMReg tempReg)
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{
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union {float f; u32 u;} conv;
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@ -93,6 +127,21 @@ void ARMXEmitter::MOVI2F(ARMReg dest, float val, ARMReg tempReg)
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// Otherwise, use a literal pool and VLDR directly (+- 1020)
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}
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void ARMXEmitter::ADDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
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{
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Operand2 op2;
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bool negated;
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if (TryMakeOperand2_AllowNegation(val, op2, &negated)) {
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if (!negated)
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ADD(rd, rs, op2);
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else
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SUB(rd, rs, op2);
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} else {
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MOVI2R(scratch, val);
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ADD(rd, rs, scratch);
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}
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}
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void ARMXEmitter::ANDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
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{
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Operand2 op2;
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@ -109,6 +158,21 @@ void ARMXEmitter::ANDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
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}
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}
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void ARMXEmitter::CMPI2R(ARMReg rs, u32 val, ARMReg scratch)
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{
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Operand2 op2;
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bool negated;
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if (TryMakeOperand2_AllowNegation(val, op2, &negated)) {
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if (!negated)
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CMP(rs, op2);
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else
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CMN(rs, op2);
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} else {
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MOVI2R(scratch, val);
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CMP(rs, scratch);
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}
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}
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void ARMXEmitter::ORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
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{
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Operand2 op2;
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@ -173,7 +237,7 @@ void ARMXEmitter::MOVI2R(ARMReg reg, u32 val, bool optimize)
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MOVW(reg, val & 0xFFFF);
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if(val & 0xFFFF0000)
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MOVT(reg, val, true);
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} else {
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} else if (!TrySetValue_TwoOp(reg,val)) {
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// Use literal pool for ARMv6.
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AddNewLit(val);
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LDR(reg, _PC); // To be backpatched later
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@ -190,9 +254,7 @@ void ARMXEmitter::SetCodePtr(u8 *ptr)
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{
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code = ptr;
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startcode = code;
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#ifdef IOS
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lastCacheFlushEnd = ptr;
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#endif
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}
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const u8 *ARMXEmitter::GetCodePtr() const
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@ -236,12 +298,9 @@ void ARMXEmitter::FlushIcacheSection(u8 *start, u8 *end)
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#elif defined(BLACKBERRY)
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msync(start, end - start, MS_SYNC | MS_INVALIDATE_ICACHE);
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#elif defined(IOS)
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if (start != NULL)
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sys_cache_control(kCacheFunctionPrepareForExecution, start, end - start);
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// Header file says this is equivalent to: sys_icache_invalidate(start, end - start);
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sys_cache_control(kCacheFunctionPrepareForExecution, start, end - start);
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#elif !defined(_WIN32)
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#ifndef ANDROID
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start = startcode; // Should be Linux Only
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#endif
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__builtin___clear_cache(start, end);
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#endif
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}
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@ -628,38 +687,40 @@ void ARMXEmitter::SVC(Operand2 op)
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// IMM, REG, IMMSREG, RSR
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// -1 for invalid if the instruction doesn't support that
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const s32 LoadStoreOps[][4] = { {0x40, 0x60, 0x60, -1}, // STR
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{0x41, 0x61, 0x61, -1}, // LDR
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{0x44, 0x64, 0x64, -1}, // STRB
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{0x45, 0x65, 0x65, -1}, // LDRB
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// Special encodings
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{ 0x4, 0x0, -1, -1}, // STRH
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{ 0x5, 0x1, -1, -1}, // LDRH
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{ 0x5, 0x1, -1, -1}, // LDRSB
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{ 0x5, 0x1, -1, -1}, // LDRSH
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};
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const char *LoadStoreNames[] = { "STR",
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"LDR",
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"STRB",
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"LDRB",
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"STRH",
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"LDRH",
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"LDRSB",
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"LDRSH",
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};
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const s32 LoadStoreOps[][4] = {
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{0x40, 0x60, 0x60, -1}, // STR
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{0x41, 0x61, 0x61, -1}, // LDR
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{0x44, 0x64, 0x64, -1}, // STRB
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{0x45, 0x65, 0x65, -1}, // LDRB
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// Special encodings
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{ 0x4, 0x0, -1, -1}, // STRH
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{ 0x5, 0x1, -1, -1}, // LDRH
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{ 0x5, 0x1, -1, -1}, // LDRSB
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{ 0x5, 0x1, -1, -1}, // LDRSH
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};
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const char *LoadStoreNames[] = {
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"STR",
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"LDR",
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"STRB",
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"LDRB",
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"STRH",
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"LDRH",
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"LDRSB",
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"LDRSH",
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};
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void ARMXEmitter::WriteStoreOp(u32 Op, ARMReg Rt, ARMReg Rn, Operand2 Rm, bool RegAdd)
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{
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s32 op = LoadStoreOps[Op][Rm.GetType()]; // Type always decided by last operand
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u32 Data;
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// Qualcomm chipsets get /really/ angry if you don't use index, even if the offset is zero.
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// Some of these encodings require Index at all times anyway. Doesn't really matter.
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// bool Index = op2 != 0 ? true : false;
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bool Index = true;
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bool Add = false;
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bool Add = false;
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// Special Encoding
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// Special Encoding (misc addressing mode)
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bool SpecialOp = false;
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bool Half = false;
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bool SignedLoad = false;
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@ -699,10 +760,13 @@ void ARMXEmitter::WriteStoreOp(u32 Op, ARMReg Rt, ARMReg Rn, Operand2 Rm, bool R
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// The offset is encoded differently on this one.
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if (SpecialOp)
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Data = (Data & 0xF0 << 4) | (Data & 0xF);
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if (Temp >= 0) Add = true;
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if (Temp >= 0) Add = true;
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}
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break;
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case TYPE_REG:
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Data = Rm.GetData();
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Add = RegAdd;
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break;
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case TYPE_IMMSREG:
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if (!SpecialOp)
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{
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@ -710,17 +774,18 @@ void ARMXEmitter::WriteStoreOp(u32 Op, ARMReg Rt, ARMReg Rn, Operand2 Rm, bool R
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Add = RegAdd;
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break;
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}
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// Intentional fallthrough: TYPE_IMMSREG not supported for misc addressing.
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default:
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// RSR not supported for any of these
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// We already have the warning above
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BKPT(0x2);
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return;
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break;
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break;
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}
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if (SpecialOp)
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{
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// Add SpecialOp things
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Data = (0x5 << 4) | (SignedLoad << 6) | (Half << 5) | Data;
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Data = (0x9 << 4) | (SignedLoad << 6) | (Half << 5) | Data;
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}
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Write32(condition | (op << 20) | (Index << 24) | (Add << 23) | (Rn << 16) | (Rt << 12) | Data);
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}
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@ -947,7 +1012,6 @@ void ARMXEmitter::VLDR(ARMReg Dest, ARMReg Base, s16 offset)
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{
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Write32(condition | (0xD << 24) | (Add << 23) | ((Dest & 0x1) << 22) | (1 << 20) | (Base << 16) \
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| ((Dest & 0x1E) << 11) | (10 << 8) | (imm >> 2));
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}
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else
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{
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@ -320,6 +320,9 @@ bool TryMakeOperand2(u32 imm, Operand2 &op2);
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bool TryMakeOperand2_AllowInverse(u32 imm, Operand2 &op2, bool *inverse);
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bool TryMakeOperand2_AllowNegation(s32 imm, Operand2 &op2, bool *negated);
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// Use this only when you know imm can be made into an Operand2.
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Operand2 AssumeMakeOperand2(u32 imm);
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inline Operand2 R(ARMReg Reg) { return Operand2(Reg, TYPE_REG); }
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inline Operand2 IMM(u32 Imm) { return Operand2(Imm, TYPE_IMM); }
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inline Operand2 Mem(void *ptr) { return Operand2((u32)ptr, TYPE_IMM); }
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@ -394,6 +397,7 @@ public:
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void FlushLitPool();
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void AddNewLit(u32 val);
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bool TrySetValue_TwoOp(ARMReg reg, u32 val);
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CCFlags GetCC() { return CCFlags(condition >> 28); }
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void SetCC(CCFlags cond = CC_AL);
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@ -562,7 +566,9 @@ public:
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void MOVI2R(ARMReg reg, u32 val, bool optimize = true);
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void MOVI2F(ARMReg dest, float val, ARMReg tempReg);
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void ADDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch);
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void ANDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch);
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void CMPI2R(ARMReg rs, u32 val, ARMReg scratch);
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void ORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch);
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