From 6cb78515c64101824d35ee7478d8d30e8dcc6879 Mon Sep 17 00:00:00 2001 From: skidau Date: Tue, 21 Dec 2010 14:48:05 +0000 Subject: [PATCH] LLE JIT: * Added 21 Arithmetic instructions to the JIT * Used the DSPAnalyser to identify arithmetic/multiplier instructions that precede a conditional branch. This allows the JIT to skip updating the SR when nothing would read from it. Marked all arithmetic/multiplier instructions in the DSPTable for this purpose. * Converted CheckExternalInterrupt into ASM * Fixed a couple instructions in DSP Load/Store git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6633 8ced0084-cf51-0410-be5f-012b33b47a6e --- Source/Core/DSPCore/Src/DSPAnalyzer.cpp | 25 +- Source/Core/DSPCore/Src/DSPAnalyzer.h | 1 + Source/Core/DSPCore/Src/DSPEmitter.cpp | 39 +- Source/Core/DSPCore/Src/DSPEmitter.h | 38 +- Source/Core/DSPCore/Src/DSPTables.cpp | 428 +++++------ Source/Core/DSPCore/Src/DSPTables.h | 1 + .../Core/DSPCore/Src/Jit/DSPJitArithmetic.cpp | 674 +++++++++++++----- Source/Core/DSPCore/Src/Jit/DSPJitCCUtil.cpp | 136 +++- .../Core/DSPCore/Src/Jit/DSPJitLoadStore.cpp | 4 +- .../Core/DSPCore/Src/Jit/DSPJitMultiplier.cpp | 57 +- Source/Core/DSPCore/Src/Jit/DSPJitUtil.cpp | 88 ++- 11 files changed, 977 insertions(+), 514 deletions(-) diff --git a/Source/Core/DSPCore/Src/DSPAnalyzer.cpp b/Source/Core/DSPCore/Src/DSPAnalyzer.cpp index 7319ba7a14..b4300867ac 100644 --- a/Source/Core/DSPCore/Src/DSPAnalyzer.cpp +++ b/Source/Core/DSPCore/Src/DSPAnalyzer.cpp @@ -85,6 +85,7 @@ void AnalyzeRange(int start_addr, int end_addr) // This may not be 100% accurate in case of jump tables! // It could get desynced, which would be bad. We'll see if that's an issue. + u16 last_arithmetic = 0; for (int addr = start_addr; addr < end_addr;) { UDSPInstruction inst = dsp_imem_read(addr); @@ -96,16 +97,32 @@ void AnalyzeRange(int start_addr, int end_addr) } code_flags[addr] |= CODE_START_OF_INST; // Look for loops. - if ((inst & 0xffe0) == 0x0060 || (inst & 0xff00) == 0x1100) { + if ((inst & 0xffe0) == 0x0060 || (inst & 0xff00) == 0x1100) + { // BLOOP, BLOOPI u16 loop_end = dsp_imem_read(addr + 1); code_flags[addr] |= CODE_LOOP_START; code_flags[loop_end] |= CODE_LOOP_END; - } else if ((inst & 0xffe0) == 0x0040 || (inst & 0xff00) == 0x1000) { + } + else if ((inst & 0xffe0) == 0x0040 || (inst & 0xff00) == 0x1000) + { // LOOP, LOOPI code_flags[addr] |= CODE_LOOP_START; code_flags[addr + 1] |= CODE_LOOP_END; } + + // Mark the last arithmetic/multiplier instruction before a branch. + // We must update the SR reg at these instructions + if (opcode->updates_sr) + { + last_arithmetic = addr; + } + + if (opcode->branch && !opcode->uncond_branch) + { + code_flags[last_arithmetic] |= CODE_UPDATE_SR; + } + addr += opcode->size; } @@ -126,12 +143,12 @@ void AnalyzeRange(int start_addr, int end_addr) } if (found) { - NOTICE_LOG(DSPLLE, "Idle skip location found at %02x (sigNum:%d)", addr, s+1); + INFO_LOG(DSPLLE, "Idle skip location found at %02x (sigNum:%d)", addr, s+1); code_flags[addr] |= CODE_IDLE_SKIP; } } } - NOTICE_LOG(DSPLLE, "Finished analysis."); + INFO_LOG(DSPLLE, "Finished analysis."); } void Analyze() diff --git a/Source/Core/DSPCore/Src/DSPAnalyzer.h b/Source/Core/DSPCore/Src/DSPAnalyzer.h index 541b76147c..6ccd8f771f 100644 --- a/Source/Core/DSPCore/Src/DSPAnalyzer.h +++ b/Source/Core/DSPCore/Src/DSPAnalyzer.h @@ -33,6 +33,7 @@ enum CODE_LOOP_START = 4, CODE_LOOP_END = 8, CODE_CALL = 16, + CODE_UPDATE_SR = 32, }; // Easy to query array covering the whole of instruction memory. diff --git a/Source/Core/DSPCore/Src/DSPEmitter.cpp b/Source/Core/DSPCore/Src/DSPEmitter.cpp index 89c2abcfa0..ea4b8a86e7 100644 --- a/Source/Core/DSPCore/Src/DSPEmitter.cpp +++ b/Source/Core/DSPCore/Src/DSPEmitter.cpp @@ -91,7 +91,7 @@ void DSPEmitter::checkExceptions(u32 retval) TEST(8, M(&g_dsp.exceptions), Imm8(0xff)); #else MOV(64, R(RAX), ImmPtr(&g_dsp.exceptions)); - TEST(8, MDisp(RAX,0), Imm8(0xff)); + TEST(8, MatR(RAX), Imm8(0xff)); #endif FixupBranch skipCheck = J_CC(CC_Z); @@ -123,7 +123,7 @@ void DSPEmitter::Default(UDSPInstruction inst) MOV(16, M(&(g_dsp.pc)), Imm16(compilePC + 1)); #else MOV(64, R(RAX), ImmPtr(&(g_dsp.pc))); - MOV(16, MDisp(RAX,0), Imm16(compilePC + 1)); + MOV(16, MatR(RAX), Imm16(compilePC + 1)); #endif } @@ -225,15 +225,6 @@ void DSPEmitter::Compile(int start_addr) // ABI_AlignStack(0); /* - // check if there is an external interrupt - if (! dsp_SR_is_flag_set(SR_EXT_INT_ENABLE)) - return; - - if (! (g_dsp.cr & CR_EXTERNAL_INT)) - return; - - g_dsp.cr &= ~CR_EXTERNAL_INT; - // Check for other exceptions if (dsp_SR_is_flag_set(SR_INT_ENABLE)) return; @@ -244,7 +235,33 @@ void DSPEmitter::Compile(int start_addr) blockLinkEntry = GetCodePtr(); +// ASM version of DSPCore_CheckExternalInterrupt. +#ifdef _M_IX86 // All32 + TEST(16, M(&g_dsp.cr), Imm16(CR_EXTERNAL_INT)); + FixupBranch noExternalInterrupt = J_CC(CC_Z); + TEST(16, M(&g_dsp.r[DSP_REG_SR]), Imm16(SR_EXT_INT_ENABLE)); + FixupBranch externalInterruptDisabled = J_CC(CC_Z); + OR(8, M(&g_dsp.exceptions), Imm8(1 << EXP_INT)); + AND(16, M(&g_dsp.cr), Imm16(~CR_EXTERNAL_INT)); + SetJumpTarget(externalInterruptDisabled); + SetJumpTarget(noExternalInterrupt); +#else + /* // TODO: Needs to be optimised + MOV(64, R(RAX), ImmPtr(&g_dsp.cr)); + TEST(16, MatR(RAX), Imm16(CR_EXTERNAL_INT)); + FixupBranch noExternalInterrupt = J_CC(CC_Z); + MOV(64, R(RAX), ImmPtr(&g_dsp.r)); + TEST(16, MDisp(RAX,DSP_REG_SR*2), Imm16(SR_EXT_INT_ENABLE)); + FixupBranch externalInterruptDisabled = J_CC(CC_Z); + MOV(64, R(RAX), ImmPtr(&g_dsp.exceptions)); + OR(8, MatR(RAX), Imm8(1 << EXP_INT)); + MOV(64, R(RAX), ImmPtr(&g_dsp.cr)); + AND(16, MatR(RAX), Imm16(~CR_EXTERNAL_INT)); + SetJumpTarget(externalInterruptDisabled); + SetJumpTarget(noExternalInterrupt); + */ ABI_CallFunction((void *)&DSPCore_CheckExternalInterrupt); +#endif compilePC = start_addr; bool fixup_pc = false; diff --git a/Source/Core/DSPCore/Src/DSPEmitter.h b/Source/Core/DSPCore/Src/DSPEmitter.h index bc3992a523..8e3bfe8da7 100644 --- a/Source/Core/DSPCore/Src/DSPEmitter.h +++ b/Source/Core/DSPCore/Src/DSPEmitter.h @@ -49,7 +49,9 @@ public: int STACKALIGN RunForCycles(int cycles); // CC Util - void Update_SR_Register64(bool carry = false, bool overflow = false); + void Update_SR_Register64(Gen::X64Reg val = Gen::EAX); + void Update_SR_Register64_Carry(Gen::X64Reg val = Gen::EAX); + void Update_SR_Register64_Carry2(Gen::X64Reg val = Gen::EAX); // Register helpers void setCompileSR(u16 bit); @@ -122,6 +124,7 @@ public: void mrr(const UDSPInstruction opc); void nx(const UDSPInstruction opc); + // Branch void jcc(const UDSPInstruction opc); void jmprcc(const UDSPInstruction opc); void call(const UDSPInstruction opc); @@ -144,9 +147,31 @@ public: void ilrri(const UDSPInstruction opc); // Arithmetic + void tst(const UDSPInstruction opc); void addr(const UDSPInstruction opc); + void addax(const UDSPInstruction opc); + void add(const UDSPInstruction opc); + void addp(const UDSPInstruction opc); + void addi(const UDSPInstruction opc); + void addis(const UDSPInstruction opc); + void incm(const UDSPInstruction opc); + void inc(const UDSPInstruction opc); + void subr(const UDSPInstruction opc); + void subax(const UDSPInstruction opc); + void sub(const UDSPInstruction opc); + void subp(const UDSPInstruction opc); + void decm(const UDSPInstruction opc); + void dec(const UDSPInstruction opc); + void neg(const UDSPInstruction opc); + void abs(const UDSPInstruction opc); + void movr(const UDSPInstruction opc); + void movax(const UDSPInstruction opc); + void mov(const UDSPInstruction opc); void lsl16(const UDSPInstruction opc); + void lsr16(const UDSPInstruction opc); + void asr16(const UDSPInstruction opc); void lsl(const UDSPInstruction opc); + void asl(const UDSPInstruction opc); // Multipliers void get_multiply_prod(); @@ -190,17 +215,20 @@ private: // Counts down. // int cycles; + void Update_SR_Register(Gen::X64Reg val = Gen::EAX); + void ToMask(Gen::X64Reg value_reg = Gen::EDI, Gen::X64Reg temp_reg = Gen::ESI); void dsp_increment_one(Gen::X64Reg ar = Gen::EAX, Gen::X64Reg wr = Gen::EDX, Gen::X64Reg wr_pow = Gen::EDI, Gen::X64Reg temp_reg = Gen::ESI); void dsp_decrement_one(Gen::X64Reg ar = Gen::EAX, Gen::X64Reg wr = Gen::EDX, Gen::X64Reg wr_pow = Gen::EDI, Gen::X64Reg temp_reg = Gen::ESI); - void get_long_prod(); - void get_long_prod_round_prodl(); + void get_long_prod(Gen::X64Reg long_prod = Gen::RAX); + void get_long_prod_round_prodl(Gen::X64Reg long_prod = Gen::RAX); void set_long_prod(); - void set_long_acc(int _reg); + void set_long_acc(int _reg, Gen::X64Reg acc = Gen::EAX); void get_acc_m(int _reg); + void get_long_acx(int _reg, Gen::X64Reg acx = Gen::EAX); void get_ax_l(int _reg); void get_ax_h(int _reg); - void get_long_acc(int _reg); + void get_long_acc(int _reg, Gen::X64Reg acc = Gen::EAX); }; diff --git a/Source/Core/DSPCore/Src/DSPTables.cpp b/Source/Core/DSPCore/Src/DSPTables.cpp index f03b6f5e92..1f5f1618f0 100644 --- a/Source/Core/DSPCore/Src/DSPTables.cpp +++ b/Source/Core/DSPCore/Src/DSPTables.cpp @@ -33,270 +33,270 @@ void nop(const UDSPInstruction opc) const DSPOPCTemplate opcodes[] = { - {"NOP", 0x0000, 0xfffc, nop, &DSPEmitter::nop, 1, 0, {}, false, false, false, false}, + {"NOP", 0x0000, 0xfffc, nop, &DSPEmitter::nop, 1, 0, {}, false, false, false, false, false}, - {"DAR", 0x0004, 0xfffc, DSPInterpreter::dar, &DSPEmitter::dar, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false}, - {"IAR", 0x0008, 0xfffc, DSPInterpreter::iar, &DSPEmitter::iar, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false}, - {"SUBARN", 0x000c, 0xfffc, DSPInterpreter::subarn, NULL/*&DSPEmitter::subarn*/, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false}, - {"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, NULL/*&DSPEmitter::addarn*/, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, false, false, false, false}, + {"DAR", 0x0004, 0xfffc, DSPInterpreter::dar, &DSPEmitter::dar, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, + {"IAR", 0x0008, 0xfffc, DSPInterpreter::iar, &DSPEmitter::iar, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, + {"SUBARN", 0x000c, 0xfffc, DSPInterpreter::subarn, NULL/*&DSPEmitter::subarn*/, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, + {"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, NULL/*&DSPEmitter::addarn*/, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, false, false, false, false, false}, - {"HALT", 0x0021, 0xffff, DSPInterpreter::halt, NULL, 1, 0, {}, false, true, true, false}, + {"HALT", 0x0021, 0xffff, DSPInterpreter::halt, NULL, 1, 0, {}, false, true, true, false, false}, - {"RETGE", 0x02d0, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true}, - {"RETL", 0x02d1, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true}, - {"RETG", 0x02d2, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true}, - {"RETLE", 0x02d3, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true}, - {"RETNZ", 0x02d4, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true}, - {"RETZ", 0x02d5, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true}, - {"RETNC", 0x02d6, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true}, - {"RETC", 0x02d7, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true}, - {"RETx8", 0x02d8, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true}, - {"RETx9", 0x02d9, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true}, - {"RETxA", 0x02da, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true}, - {"RETxB", 0x02db, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true}, - {"RETLNZ", 0x02dc, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true}, - {"RETLZ", 0x02dd, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true}, - {"RETO", 0x02de, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true}, - {"RET", 0x02df, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, true, false}, + {"RETGE", 0x02d0, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true, false}, + {"RETL", 0x02d1, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true, false}, + {"RETG", 0x02d2, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true, false}, + {"RETLE", 0x02d3, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true, false}, + {"RETNZ", 0x02d4, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true, false}, + {"RETZ", 0x02d5, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true, false}, + {"RETNC", 0x02d6, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true, false}, + {"RETC", 0x02d7, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true, false}, + {"RETx8", 0x02d8, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true, false}, + {"RETx9", 0x02d9, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true, false}, + {"RETxA", 0x02da, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true, false}, + {"RETxB", 0x02db, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true, false}, + {"RETLNZ", 0x02dc, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true, false}, + {"RETLZ", 0x02dd, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true, false}, + {"RETO", 0x02de, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false, true, false}, + {"RET", 0x02df, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, true, false, false}, - {"RTI", 0x02ff, 0xffff, DSPInterpreter::rti, NULL, 1, 0, {}, false, true, true, false}, + {"RTI", 0x02ff, 0xffff, DSPInterpreter::rti, NULL, 1, 0, {}, false, true, true, false, false}, - {"CALLGE", 0x02b0, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"CALLL", 0x02b1, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"CALLG", 0x02b2, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"CALLLE", 0x02b3, 0xffff, DSPInterpreter::call, NULL/*&DSPEmitter::call*/, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"CALLNZ", 0x02b4, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"CALLZ", 0x02b5, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"CALLNC", 0x02b6, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"CALLC", 0x02b7, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"CALLx8", 0x02b8, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"CALLx9", 0x02b9, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"CALLxA", 0x02ba, 0xffff, DSPInterpreter::call, NULL/*&DSPEmitter::call*/, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"CALLxB", 0x02bb, 0xffff, DSPInterpreter::call, NULL/*&DSPEmitter::call*/, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"CALLLNZ", 0x02bc, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"CALLLZ", 0x02bd, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"CALLO", 0x02be, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"CALL", 0x02bf, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true}, + {"CALLGE", 0x02b0, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"CALLL", 0x02b1, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"CALLG", 0x02b2, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"CALLLE", 0x02b3, 0xffff, DSPInterpreter::call, NULL/*&DSPEmitter::call*/, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"CALLNZ", 0x02b4, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"CALLZ", 0x02b5, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"CALLNC", 0x02b6, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"CALLC", 0x02b7, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"CALLx8", 0x02b8, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"CALLx9", 0x02b9, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"CALLxA", 0x02ba, 0xffff, DSPInterpreter::call, NULL/*&DSPEmitter::call*/, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"CALLxB", 0x02bb, 0xffff, DSPInterpreter::call, NULL/*&DSPEmitter::call*/, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"CALLLNZ", 0x02bc, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"CALLLZ", 0x02bd, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"CALLO", 0x02be, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"CALL", 0x02bf, 0xffff, DSPInterpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true, false}, - {"IFGE", 0x0270, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true}, - {"IFL", 0x0271, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true}, - {"IFG", 0x0272, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true}, - {"IFLE", 0x0273, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true}, - {"IFNZ", 0x0274, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true}, - {"IFZ", 0x0275, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true}, - {"IFNC", 0x0276, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true}, - {"IFC", 0x0277, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true}, - {"IFx8", 0x0278, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true}, - {"IFx9", 0x0279, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true}, - {"IFxA", 0x027a, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true}, - {"IFxB", 0x027b, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true}, - {"IFLNZ", 0x027c, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true}, - {"IFLZ", 0x027d, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true}, - {"IFO", 0x027e, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true}, - {"IF", 0x027f, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, true, true}, + {"IFGE", 0x0270, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true, false}, + {"IFL", 0x0271, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true, false}, + {"IFG", 0x0272, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true, false}, + {"IFLE", 0x0273, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true, false}, + {"IFNZ", 0x0274, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true, false}, + {"IFZ", 0x0275, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true, false}, + {"IFNC", 0x0276, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true, false}, + {"IFC", 0x0277, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true, false}, + {"IFx8", 0x0278, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true, false}, + {"IFx9", 0x0279, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true, false}, + {"IFxA", 0x027a, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true, false}, + {"IFxB", 0x027b, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true, false}, + {"IFLNZ", 0x027c, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true, false}, + {"IFLZ", 0x027d, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true, false}, + {"IFO", 0x027e, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false, true, false}, + {"IF", 0x027f, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, true, true, false}, - {"JGE", 0x0290, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"JL", 0x0291, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"JG", 0x0292, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"JLE", 0x0293, 0xffff, DSPInterpreter::jcc, NULL/*&DSPEmitter::jcc*/, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"JNZ", 0x0294, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"JZ", 0x0295, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"JNC", 0x0296, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"JC", 0x0297, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"JMPx8", 0x0298, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"JMPx9", 0x0299, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"JMPxA", 0x029a, 0xffff, DSPInterpreter::jcc, NULL/*&DSPEmitter::jcc*/, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"JMPxB", 0x029b, 0xffff, DSPInterpreter::jcc, NULL/*&DSPEmitter::jcc*/, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"JLNZ", 0x029c, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"JLZ", 0x029d, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"JO", 0x029e, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"JMP", 0x029f, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true}, + {"JGE", 0x0290, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"JL", 0x0291, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"JG", 0x0292, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"JLE", 0x0293, 0xffff, DSPInterpreter::jcc, NULL/*&DSPEmitter::jcc*/, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"JNZ", 0x0294, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"JZ", 0x0295, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"JNC", 0x0296, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"JC", 0x0297, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"JMPx8", 0x0298, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"JMPx9", 0x0299, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"JMPxA", 0x029a, 0xffff, DSPInterpreter::jcc, NULL/*&DSPEmitter::jcc*/, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"JMPxB", 0x029b, 0xffff, DSPInterpreter::jcc, NULL/*&DSPEmitter::jcc*/, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"JLNZ", 0x029c, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"JLZ", 0x029d, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"JO", 0x029e, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"JMP", 0x029f, 0xffff, DSPInterpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true, false}, - {"JRGE", 0x1700, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false}, - {"JRL", 0x1701, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false}, - {"JRG", 0x1702, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false}, - {"JRLE", 0x1703, 0xff1f, DSPInterpreter::jmprcc, NULL/*&DSPEmitter::jmprcc*/, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false}, - {"JRNZ", 0x1704, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false}, - {"JRZ", 0x1705, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false}, - {"JRNC", 0x1706, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false}, - {"JRC", 0x1707, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false}, - {"JMPRx8", 0x1708, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false}, - {"JMPRx9", 0x1709, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false}, - {"JMPRxA", 0x170a, 0xff1f, DSPInterpreter::jmprcc, NULL/*&DSPEmitter::jmprcc*/, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false}, - {"JMPRxB", 0x170b, 0xff1f, DSPInterpreter::jmprcc, NULL/*&DSPEmitter::jmprcc*/, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false}, - {"JRLNZ", 0x170c, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false}, - {"JRLZ", 0x170d, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false}, - {"JRO", 0x170e, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false}, - {"JMPR", 0x170f, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, true, false}, + {"JRGE", 0x1700, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, + {"JRL", 0x1701, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, + {"JRG", 0x1702, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, + {"JRLE", 0x1703, 0xff1f, DSPInterpreter::jmprcc, NULL/*&DSPEmitter::jmprcc*/, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, + {"JRNZ", 0x1704, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, + {"JRZ", 0x1705, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, + {"JRNC", 0x1706, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, + {"JRC", 0x1707, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, + {"JMPRx8", 0x1708, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, + {"JMPRx9", 0x1709, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, + {"JMPRxA", 0x170a, 0xff1f, DSPInterpreter::jmprcc, NULL/*&DSPEmitter::jmprcc*/, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, + {"JMPRxB", 0x170b, 0xff1f, DSPInterpreter::jmprcc, NULL/*&DSPEmitter::jmprcc*/, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, + {"JRLNZ", 0x170c, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, + {"JRLZ", 0x170d, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, + {"JRO", 0x170e, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, + {"JMPR", 0x170f, 0xff1f, DSPInterpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, true, false, false}, - {"CALLRGE", 0x1710, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true}, - {"CALLRL", 0x1711, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true}, - {"CALLRG", 0x1712, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true}, - {"CALLRLE", 0x1713, 0xff1f, DSPInterpreter::callr, NULL/*&DSPEmitter::callr*/, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true}, - {"CALLRNZ", 0x1714, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true}, - {"CALLRZ", 0x1715, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true}, - {"CALLRNC", 0x1716, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true}, - {"CALLRC", 0x1717, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true}, - {"CALLRx8", 0x1718, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true}, - {"CALLRx9", 0x1719, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true}, - {"CALLRxA", 0x171a, 0xff1f, DSPInterpreter::callr, NULL/*&DSPEmitter::callr*/, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true}, - {"CALLRxB", 0x171b, 0xff1f, DSPInterpreter::callr, NULL/*&DSPEmitter::callr*/, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true}, - {"CALLRLNZ",0x171c, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true}, - {"CALLRLZ", 0x171d, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true}, - {"CALLRO", 0x171e, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true}, - {"CALLR", 0x171f, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, true, true}, + {"CALLRGE", 0x1710, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, + {"CALLRL", 0x1711, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, + {"CALLRG", 0x1712, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, + {"CALLRLE", 0x1713, 0xff1f, DSPInterpreter::callr, NULL/*&DSPEmitter::callr*/, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, + {"CALLRNZ", 0x1714, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, + {"CALLRZ", 0x1715, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, + {"CALLRNC", 0x1716, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, + {"CALLRC", 0x1717, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, + {"CALLRx8", 0x1718, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, + {"CALLRx9", 0x1719, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, + {"CALLRxA", 0x171a, 0xff1f, DSPInterpreter::callr, NULL/*&DSPEmitter::callr*/, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, + {"CALLRxB", 0x171b, 0xff1f, DSPInterpreter::callr, NULL/*&DSPEmitter::callr*/, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, + {"CALLRLNZ",0x171c, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, + {"CALLRLZ", 0x171d, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, + {"CALLRO", 0x171e, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, + {"CALLR", 0x171f, 0xff1f, DSPInterpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, true, true, false}, - {"SBCLR", 0x1200, 0xff00, DSPInterpreter::sbclr, &DSPEmitter::sbclr, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false, false, false}, - {"SBSET", 0x1300, 0xff00, DSPInterpreter::sbset, &DSPEmitter::sbset, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false, false, false}, + {"SBCLR", 0x1200, 0xff00, DSPInterpreter::sbclr, &DSPEmitter::sbclr, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false, false, false, false}, + {"SBSET", 0x1300, 0xff00, DSPInterpreter::sbset, &DSPEmitter::sbset, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false, false, false, false}, - {"LSL", 0x1400, 0xfec0, DSPInterpreter::lsl, &DSPEmitter::lsl, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false}, - {"LSR", 0x1440, 0xfec0, DSPInterpreter::lsr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false}, - {"ASL", 0x1480, 0xfec0, DSPInterpreter::asl, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false}, - {"ASR", 0x14c0, 0xfec0, DSPInterpreter::asr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false}, + {"LSL", 0x1400, 0xfec0, DSPInterpreter::lsl, &DSPEmitter::lsl, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, + {"LSR", 0x1440, 0xfec0, DSPInterpreter::lsr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, + {"ASL", 0x1480, 0xfec0, DSPInterpreter::asl, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, + {"ASR", 0x14c0, 0xfec0, DSPInterpreter::asr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, - {"LSRN", 0x02ca, 0xffff, DSPInterpreter::lsrn, NULL, 1, 0, {}, false, false, false, false}, // discovered by ector! - {"ASRN", 0x02cb, 0xffff, DSPInterpreter::asrn, NULL, 1, 0, {}, false, false, false, false}, // discovered by ector! + {"LSRN", 0x02ca, 0xffff, DSPInterpreter::lsrn, NULL, 1, 0, {}, false, false, false, false, true}, // discovered by ector! + {"ASRN", 0x02cb, 0xffff, DSPInterpreter::asrn, NULL, 1, 0, {}, false, false, false, false, true}, // discovered by ector! - {"LRI", 0x0080, 0xffe0, DSPInterpreter::lri, &DSPEmitter::lri, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true}, - {"LR", 0x00c0, 0xffe0, DSPInterpreter::lr, &DSPEmitter::lr, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_MEM, 2, 1, 0, 0xffff}}, false, false, false, true}, - {"SR", 0x00e0, 0xffe0, DSPInterpreter::sr, &DSPEmitter::sr, 2, 2, {{P_MEM, 2, 1, 0, 0xffff}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, true}, + {"LRI", 0x0080, 0xffe0, DSPInterpreter::lri, &DSPEmitter::lri, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, false}, + {"LR", 0x00c0, 0xffe0, DSPInterpreter::lr, &DSPEmitter::lr, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_MEM, 2, 1, 0, 0xffff}}, false, false, false, true, false}, + {"SR", 0x00e0, 0xffe0, DSPInterpreter::sr, &DSPEmitter::sr, 2, 2, {{P_MEM, 2, 1, 0, 0xffff}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, true, false}, - {"MRR", 0x1c00, 0xfc00, DSPInterpreter::mrr, &DSPEmitter::mrr, 1, 2, {{P_REG, 1, 0, 5, 0x03e0}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false}, + {"MRR", 0x1c00, 0xfc00, DSPInterpreter::mrr, &DSPEmitter::mrr, 1, 2, {{P_REG, 1, 0, 5, 0x03e0}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, - {"SI", 0x1600, 0xff00, DSPInterpreter::si, &DSPEmitter::si, 2, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true}, + {"SI", 0x1600, 0xff00, DSPInterpreter::si, &DSPEmitter::si, 2, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, false}, - {"ADDIS", 0x0400, 0xfe00, DSPInterpreter::addis, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false, false}, - {"CMPIS", 0x0600, 0xfe00, DSPInterpreter::cmpis, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false, false}, - {"LRIS", 0x0800, 0xf800, DSPInterpreter::lris, &DSPEmitter::lris, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false, false}, + {"ADDIS", 0x0400, 0xfe00, DSPInterpreter::addis, &DSPEmitter::addis, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false, false, true}, + {"CMPIS", 0x0600, 0xfe00, DSPInterpreter::cmpis, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false, false, true}, + {"LRIS", 0x0800, 0xf800, DSPInterpreter::lris, &DSPEmitter::lris, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false, false, true}, - {"ADDI", 0x0200, 0xfeff, DSPInterpreter::addi, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true}, - {"XORI", 0x0220, 0xfeff, DSPInterpreter::xori, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true}, - {"ANDI", 0x0240, 0xfeff, DSPInterpreter::andi, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true}, - {"ORI", 0x0260, 0xfeff, DSPInterpreter::ori, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true}, - {"CMPI", 0x0280, 0xfeff, DSPInterpreter::cmpi, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true}, + {"ADDI", 0x0200, 0xfeff, DSPInterpreter::addi, &DSPEmitter::addi, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, + {"XORI", 0x0220, 0xfeff, DSPInterpreter::xori, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, + {"ANDI", 0x0240, 0xfeff, DSPInterpreter::andi, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, + {"ORI", 0x0260, 0xfeff, DSPInterpreter::ori, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, + {"CMPI", 0x0280, 0xfeff, DSPInterpreter::cmpi, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, - {"ANDF", 0x02a0, 0xfeff, DSPInterpreter::andf, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true}, - {"ANDCF", 0x02c0, 0xfeff, DSPInterpreter::andcf, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true}, + {"ANDF", 0x02a0, 0xfeff, DSPInterpreter::andf, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, + {"ANDCF", 0x02c0, 0xfeff, DSPInterpreter::andcf, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, - {"ILRR", 0x0210, 0xfefc, DSPInterpreter::ilrr, &DSPEmitter::ilrr, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false}, - {"ILRRD", 0x0214, 0xfefc, DSPInterpreter::ilrrd, &DSPEmitter::ilrrd, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false}, - {"ILRRI", 0x0218, 0xfefc, DSPInterpreter::ilrri, &DSPEmitter::ilrri, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false}, - {"ILRRN", 0x021c, 0xfefc, DSPInterpreter::ilrrn, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false}, + {"ILRR", 0x0210, 0xfefc, DSPInterpreter::ilrr, &DSPEmitter::ilrr, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, + {"ILRRD", 0x0214, 0xfefc, DSPInterpreter::ilrrd, &DSPEmitter::ilrrd, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, + {"ILRRI", 0x0218, 0xfefc, DSPInterpreter::ilrri, &DSPEmitter::ilrri, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, + {"ILRRN", 0x021c, 0xfefc, DSPInterpreter::ilrrn, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // LOOPS - {"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, NULL, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, false, true, false, true}, - {"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, NULL, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, - {"LOOPI", 0x1000, 0xff00, DSPInterpreter::loopi, NULL, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}}, false, true, false, true}, - {"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, NULL, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true}, + {"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, NULL, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, false, true, false, true, false}, + {"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, NULL, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, + {"LOOPI", 0x1000, 0xff00, DSPInterpreter::loopi, NULL, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}}, false, true, false, true, false}, + {"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, NULL, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // load and store value pointed by indexing reg and increment; LRR/SRR variants - {"LRR", 0x1800, 0xff80, DSPInterpreter::lrr, &DSPEmitter::lrr, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false}, - {"LRRD", 0x1880, 0xff80, DSPInterpreter::lrrd, &DSPEmitter::lrrd, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false}, - {"LRRI", 0x1900, 0xff80, DSPInterpreter::lrri, &DSPEmitter::lrri, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false}, - {"LRRN", 0x1980, 0xff80, DSPInterpreter::lrrn, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false}, + {"LRR", 0x1800, 0xff80, DSPInterpreter::lrr, &DSPEmitter::lrr, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, + {"LRRD", 0x1880, 0xff80, DSPInterpreter::lrrd, &DSPEmitter::lrrd, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, + {"LRRI", 0x1900, 0xff80, DSPInterpreter::lrri, &DSPEmitter::lrri, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, + {"LRRN", 0x1980, 0xff80, DSPInterpreter::lrrn, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, - {"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, &DSPEmitter::srr, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false}, - {"SRRD", 0x1a80, 0xff80, DSPInterpreter::srrd, &DSPEmitter::srrd, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false}, - {"SRRI", 0x1b00, 0xff80, DSPInterpreter::srri, &DSPEmitter::srri, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false}, - {"SRRN", 0x1b80, 0xff80, DSPInterpreter::srrn, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false}, + {"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, &DSPEmitter::srr, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, + {"SRRD", 0x1a80, 0xff80, DSPInterpreter::srrd, &DSPEmitter::srrd, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, + {"SRRI", 0x1b00, 0xff80, DSPInterpreter::srri, &DSPEmitter::srri, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, + {"SRRN", 0x1b80, 0xff80, DSPInterpreter::srrn, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, //2 - {"LRS", 0x2000, 0xf800, DSPInterpreter::lrs, &DSPEmitter::lrs, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_MEM, 1, 0, 0, 0x00ff}}, false, false, false, false}, - {"SRS", 0x2800, 0xf800, DSPInterpreter::srs, &DSPEmitter::srs, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG18, 1, 0, 8, 0x0700}}, false, false, false, false}, + {"LRS", 0x2000, 0xf800, DSPInterpreter::lrs, &DSPEmitter::lrs, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_MEM, 1, 0, 0, 0x00ff}}, false, false, false, false, false}, + {"SRS", 0x2800, 0xf800, DSPInterpreter::srs, &DSPEmitter::srs, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG18, 1, 0, 8, 0x0700}}, false, false, false, false, false}, // opcodes that can be extended //3 - main opcode defined by 9 bits, extension defined by last 7 bits!! - {"XORR", 0x3000, 0xfc80, DSPInterpreter::xorr, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false}, - {"ANDR", 0x3400, 0xfc80, DSPInterpreter::andr, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false}, - {"ORR", 0x3800, 0xfc80, DSPInterpreter::orr, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false}, - {"ANDC", 0x3c00, 0xfe80, DSPInterpreter::andc, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"ORC", 0x3e00, 0xfe80, DSPInterpreter::orc, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"XORC", 0x3080, 0xfe80, DSPInterpreter::xorc, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"NOT", 0x3280, 0xfe80, DSPInterpreter::notc, NULL, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"LSRNRX", 0x3480, 0xfc80, DSPInterpreter::lsrnrx, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false}, - {"ASRNRX", 0x3880, 0xfc80, DSPInterpreter::asrnrx, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false}, - {"LSRNR", 0x3c80, 0xfe80, DSPInterpreter::lsrnr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"ASRNR", 0x3e80, 0xfe80, DSPInterpreter::asrnr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false}, + {"XORR", 0x3000, 0xfc80, DSPInterpreter::xorr, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, + {"ANDR", 0x3400, 0xfc80, DSPInterpreter::andr, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, + {"ORR", 0x3800, 0xfc80, DSPInterpreter::orr, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, + {"ANDC", 0x3c00, 0xfe80, DSPInterpreter::andc, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"ORC", 0x3e00, 0xfe80, DSPInterpreter::orc, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"XORC", 0x3080, 0xfe80, DSPInterpreter::xorc, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"NOT", 0x3280, 0xfe80, DSPInterpreter::notc, NULL, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"LSRNRX", 0x3480, 0xfc80, DSPInterpreter::lsrnrx, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, + {"ASRNRX", 0x3880, 0xfc80, DSPInterpreter::asrnrx, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, + {"LSRNR", 0x3c80, 0xfe80, DSPInterpreter::lsrnr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"ASRNR", 0x3e80, 0xfe80, DSPInterpreter::asrnr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, //4 - {"ADDR", 0x4000, 0xf800, DSPInterpreter::addr, &DSPEmitter::addr, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false, false}, - {"ADDAX", 0x4800, 0xfc00, DSPInterpreter::addax, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false, false}, - {"ADD", 0x4c00, 0xfe00, DSPInterpreter::add, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"ADDP", 0x4e00, 0xfe00, DSPInterpreter::addp, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, + {"ADDR", 0x4000, 0xf800, DSPInterpreter::addr, &DSPEmitter::addr, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false, false, true}, + {"ADDAX", 0x4800, 0xfc00, DSPInterpreter::addax, &DSPEmitter::addax, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false, false, true}, + {"ADD", 0x4c00, 0xfe00, DSPInterpreter::add, &DSPEmitter::add, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"ADDP", 0x4e00, 0xfe00, DSPInterpreter::addp, &DSPEmitter::addp, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, //5 - {"SUBR", 0x5000, 0xf800, DSPInterpreter::subr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false, false}, - {"SUBAX", 0x5800, 0xfc00, DSPInterpreter::subax, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false, false}, - {"SUB", 0x5c00, 0xfe00, DSPInterpreter::sub, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"SUBP", 0x5e00, 0xfe00, DSPInterpreter::subp, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, + {"SUBR", 0x5000, 0xf800, DSPInterpreter::subr, &DSPEmitter::subr, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false, false, true}, + {"SUBAX", 0x5800, 0xfc00, DSPInterpreter::subax, &DSPEmitter::subax, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false, false, true}, + {"SUB", 0x5c00, 0xfe00, DSPInterpreter::sub, &DSPEmitter::sub, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"SUBP", 0x5e00, 0xfe00, DSPInterpreter::subp, &DSPEmitter::subp, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, //6 - {"MOVR", 0x6000, 0xf800, DSPInterpreter::movr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false, false}, - {"MOVAX", 0x6800, 0xfc00, DSPInterpreter::movax, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false, false}, - {"MOV", 0x6c00, 0xfe00, DSPInterpreter::mov, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"MOVP", 0x6e00, 0xfe00, DSPInterpreter::movp, &DSPEmitter::movp, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, + {"MOVR", 0x6000, 0xf800, DSPInterpreter::movr, &DSPEmitter::movr, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false, false, true}, + {"MOVAX", 0x6800, 0xfc00, DSPInterpreter::movax, &DSPEmitter::movax, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false, false, true}, + {"MOV", 0x6c00, 0xfe00, DSPInterpreter::mov, &DSPEmitter::mov, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"MOVP", 0x6e00, 0xfe00, DSPInterpreter::movp, &DSPEmitter::movp, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, //7 - {"ADDAXL", 0x7000, 0xfc00, DSPInterpreter::addaxl, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true, false, false, false}, - {"INCM", 0x7400, 0xfe00, DSPInterpreter::incm, NULL, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"INC", 0x7600, 0xfe00, DSPInterpreter::inc, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"DECM", 0x7800, 0xfe00, DSPInterpreter::decm, NULL, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"DEC", 0x7a00, 0xfe00, DSPInterpreter::dec, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"NEG", 0x7c00, 0xfe00, DSPInterpreter::neg, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"MOVNP", 0x7e00, 0xfe00, DSPInterpreter::movnp, &DSPEmitter::movnp, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, + {"ADDAXL", 0x7000, 0xfc00, DSPInterpreter::addaxl, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true, false, false, false, true}, + {"INCM", 0x7400, 0xfe00, DSPInterpreter::incm, &DSPEmitter::incm, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"INC", 0x7600, 0xfe00, DSPInterpreter::inc, &DSPEmitter::inc, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"DECM", 0x7800, 0xfe00, DSPInterpreter::decm, &DSPEmitter::decm, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"DEC", 0x7a00, 0xfe00, DSPInterpreter::dec, &DSPEmitter::dec, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"NEG", 0x7c00, 0xfe00, DSPInterpreter::neg, &DSPEmitter::neg, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"MOVNP", 0x7e00, 0xfe00, DSPInterpreter::movnp, &DSPEmitter::movnp, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, //8 - {"NX", 0x8000, 0xf700, DSPInterpreter::nx, &DSPEmitter::nx, 1, 0, {}, true, false, false, false}, - {"CLR", 0x8100, 0xf700, DSPInterpreter::clr, NULL, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false}, - {"CMP", 0x8200, 0xff00, DSPInterpreter::cmp, NULL, 1, 0, {}, true, false, false, false}, - {"MULAXH", 0x8300, 0xff00, DSPInterpreter::mulaxh, &DSPEmitter::mulaxh, 1, 0, {}, true, false, false, false}, - {"CLRP", 0x8400, 0xff00, DSPInterpreter::clrp, &DSPEmitter::clrp, 1, 0, {}, true, false, false, false}, - {"TSTPROD", 0x8500, 0xff00, DSPInterpreter::tstprod, &DSPEmitter::tstprod,1, 0, {}, true, false, false, false}, - {"TSTAXH", 0x8600, 0xfe00, DSPInterpreter::tstaxh, NULL, 1, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"M2", 0x8a00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false}, - {"M0", 0x8b00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false}, - {"CLR15", 0x8c00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false}, - {"SET15", 0x8d00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false}, - {"SET16", 0x8e00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false}, - {"SET40", 0x8f00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false}, + {"NX", 0x8000, 0xf700, DSPInterpreter::nx, &DSPEmitter::nx, 1, 0, {}, true, false, false, false, false}, + {"CLR", 0x8100, 0xf700, DSPInterpreter::clr, NULL, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, + {"CMP", 0x8200, 0xff00, DSPInterpreter::cmp, NULL, 1, 0, {}, true, false, false, false, true}, + {"MULAXH", 0x8300, 0xff00, DSPInterpreter::mulaxh, &DSPEmitter::mulaxh, 1, 0, {}, true, false, false, false, true}, + {"CLRP", 0x8400, 0xff00, DSPInterpreter::clrp, &DSPEmitter::clrp, 1, 0, {}, true, false, false, false, true}, + {"TSTPROD", 0x8500, 0xff00, DSPInterpreter::tstprod, &DSPEmitter::tstprod,1, 0, {}, true, false, false, false, true}, + {"TSTAXH", 0x8600, 0xfe00, DSPInterpreter::tstaxh, NULL, 1, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"M2", 0x8a00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false, false}, + {"M0", 0x8b00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false, false}, + {"CLR15", 0x8c00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false, false}, + {"SET15", 0x8d00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false, false}, + {"SET16", 0x8e00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false, false}, + {"SET40", 0x8f00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false, false}, //9 - {"MUL", 0x9000, 0xf700, DSPInterpreter::mul, &DSPEmitter::mul, 1, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false, false, false}, - {"ASR16", 0x9100, 0xf700, DSPInterpreter::asr16, NULL, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false}, - {"MULMVZ", 0x9200, 0xf600, DSPInterpreter::mulmvz, &DSPEmitter::mulmvz, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"MULAC", 0x9400, 0xf600, DSPInterpreter::mulac, &DSPEmitter::mulac, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"MULMV", 0x9600, 0xf600, DSPInterpreter::mulmv, &DSPEmitter::mulmv, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, + {"MUL", 0x9000, 0xf700, DSPInterpreter::mul, &DSPEmitter::mul, 1, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false, false, false, true}, + {"ASR16", 0x9100, 0xf700, DSPInterpreter::asr16, &DSPEmitter::asr16, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, + {"MULMVZ", 0x9200, 0xf600, DSPInterpreter::mulmvz, &DSPEmitter::mulmvz, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"MULAC", 0x9400, 0xf600, DSPInterpreter::mulac, &DSPEmitter::mulac, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"MULMV", 0x9600, 0xf600, DSPInterpreter::mulmv, &DSPEmitter::mulmv, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, //a-b - {"MULX", 0xa000, 0xe700, DSPInterpreter::mulx, NULL, 1, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true, false, false, false}, - {"ABS", 0xa100, 0xf700, DSPInterpreter::abs, NULL, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false}, - {"MULXMVZ", 0xa200, 0xe600, DSPInterpreter::mulxmvz, NULL, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"MULXAC", 0xa400, 0xe600, DSPInterpreter::mulxac, NULL, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"MULXMV", 0xa600, 0xe600, DSPInterpreter::mulxmv, NULL, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"TST", 0xb100, 0xf700, DSPInterpreter::tst, NULL, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false}, + {"MULX", 0xa000, 0xe700, DSPInterpreter::mulx, NULL, 1, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true, false, false, false, true}, + {"ABS", 0xa100, 0xf700, DSPInterpreter::abs, &DSPEmitter::abs, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, + {"MULXMVZ", 0xa200, 0xe600, DSPInterpreter::mulxmvz, NULL, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"MULXAC", 0xa400, 0xe600, DSPInterpreter::mulxac, NULL, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"MULXMV", 0xa600, 0xe600, DSPInterpreter::mulxmv, NULL, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"TST", 0xb100, 0xf700, DSPInterpreter::tst, &DSPEmitter::tst, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, //c-d - {"MULC", 0xc000, 0xe700, DSPInterpreter::mulc, &DSPEmitter::mulc, 1, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false, false, false}, - {"CMPAR" , 0xc100, 0xe700, DSPInterpreter::cmpar, NULL, 1, 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false, false, false}, - {"MULCMVZ", 0xc200, 0xe600, DSPInterpreter::mulcmvz, &DSPEmitter::mulcmvz,1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"MULCAC", 0xc400, 0xe600, DSPInterpreter::mulcac, &DSPEmitter::mulcac, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"MULCMV", 0xc600, 0xe600, DSPInterpreter::mulcmv, &DSPEmitter::mulcmv, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, + {"MULC", 0xc000, 0xe700, DSPInterpreter::mulc, &DSPEmitter::mulc, 1, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false, false, false, true}, + {"CMPAR" , 0xc100, 0xe700, DSPInterpreter::cmpar, NULL, 1, 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false, false, false, true}, + {"MULCMVZ", 0xc200, 0xe600, DSPInterpreter::mulcmvz, &DSPEmitter::mulcmvz,1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"MULCAC", 0xc400, 0xe600, DSPInterpreter::mulcac, &DSPEmitter::mulcac, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"MULCMV", 0xc600, 0xe600, DSPInterpreter::mulcmv, &DSPEmitter::mulcmv, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, //e - {"MADDX", 0xe000, 0xfc00, DSPInterpreter::maddx, NULL, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false, false, false}, - {"MSUBX", 0xe400, 0xfc00, DSPInterpreter::msubx, NULL, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false, false, false}, - {"MADDC", 0xe800, 0xfc00, DSPInterpreter::maddc, &DSPEmitter::maddc, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false, false, false}, - {"MSUBC", 0xec00, 0xfc00, DSPInterpreter::msubc, &DSPEmitter::msubc, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false, false, false}, + {"MADDX", 0xe000, 0xfc00, DSPInterpreter::maddx, NULL, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, + {"MSUBX", 0xe400, 0xfc00, DSPInterpreter::msubx, NULL, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, + {"MADDC", 0xe800, 0xfc00, DSPInterpreter::maddc, &DSPEmitter::maddc, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, + {"MSUBC", 0xec00, 0xfc00, DSPInterpreter::msubc, &DSPEmitter::msubc, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, //f - {"LSL16", 0xf000, 0xfe00, DSPInterpreter::lsl16, &DSPEmitter::lsl16, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"MADD", 0xf200, 0xfe00, DSPInterpreter::madd, &DSPEmitter::madd, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"LSR16", 0xf400, 0xfe00, DSPInterpreter::lsr16, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"MSUB", 0xf600, 0xfe00, DSPInterpreter::msub, &DSPEmitter::msub, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"ADDPAXZ", 0xf800, 0xfc00, DSPInterpreter::addpaxz, NULL, 1, 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_AX, 1, 0, 8, 0x0100}}, true, false, false, false}, - {"CLRL", 0xfc00, 0xfe00, DSPInterpreter::clrl, NULL, 1, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true, false, false, false}, - {"MOVPZ", 0xfe00, 0xfe00, DSPInterpreter::movpz, &DSPEmitter::movpz, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false}, + {"LSL16", 0xf000, 0xfe00, DSPInterpreter::lsl16, &DSPEmitter::lsl16, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"MADD", 0xf200, 0xfe00, DSPInterpreter::madd, &DSPEmitter::madd, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"LSR16", 0xf400, 0xfe00, DSPInterpreter::lsr16, &DSPEmitter::lsl16, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"MSUB", 0xf600, 0xfe00, DSPInterpreter::msub, &DSPEmitter::msub, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"ADDPAXZ", 0xf800, 0xfc00, DSPInterpreter::addpaxz, NULL, 1, 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_AX, 1, 0, 8, 0x0100}}, true, false, false, false, true}, + {"CLRL", 0xfc00, 0xfe00, DSPInterpreter::clrl, NULL, 1, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true, false, false, false, true}, + {"MOVPZ", 0xfe00, 0xfe00, DSPInterpreter::movpz, &DSPEmitter::movpz, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, }; const DSPOPCTemplate cw = diff --git a/Source/Core/DSPCore/Src/DSPTables.h b/Source/Core/DSPCore/Src/DSPTables.h index e8c42c73fd..56ad885d23 100644 --- a/Source/Core/DSPCore/Src/DSPTables.h +++ b/Source/Core/DSPCore/Src/DSPTables.h @@ -97,6 +97,7 @@ typedef struct bool branch; bool uncond_branch; bool reads_pc; + bool updates_sr; } DSPOPCTemplate; typedef DSPOPCTemplate opc_t; diff --git a/Source/Core/DSPCore/Src/Jit/DSPJitArithmetic.cpp b/Source/Core/DSPCore/Src/Jit/DSPJitArithmetic.cpp index 3278f6f26e..627f902aab 100644 --- a/Source/Core/DSPCore/Src/Jit/DSPJitArithmetic.cpp +++ b/Source/Core/DSPCore/Src/Jit/DSPJitArithmetic.cpp @@ -20,6 +20,7 @@ #include "../DSPIntCCUtil.h" #include "../DSPIntUtil.h" #include "../DSPEmitter.h" +#include "../DSPAnalyzer.h" #include "x64Emitter.h" #include "ABI.h" using namespace Gen; @@ -96,14 +97,21 @@ using namespace Gen; // Test accumulator %acR. // // flags out: --xx xx00 -//void DSPEmitter::tst(const UDSPInstruction opc) -//{ -// u8 reg = (opc >> 11) & 0x1; - -// s64 acc = dsp_get_long_acc(reg); -// Update_SR_Register64(acc); -// zeroWriteBackLog(); -//} +void DSPEmitter::tst(const UDSPInstruction opc) +{ +#ifdef _M_X64 + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + u8 reg = (opc >> 11) & 0x1; +// s64 acc = dsp_get_long_acc(reg); + get_long_acc(reg); +// Update_SR_Register64(acc); + Update_SR_Register64(); + } +#else + Default(opc); +#endif +} // TSTAXH $axR.h // 1000 011r xxxx xxxx @@ -383,8 +391,8 @@ void DSPEmitter::addr(const UDSPInstruction opc) MOV(64, R(R11), ImmPtr(&g_dsp.r)); // s64 acc = dsp_get_long_acc(dreg); - get_long_acc(dreg); - PUSH(64, R(RAX)); + get_long_acc(dreg, RCX); + MOV(64, R(RAX), R(RCX)); // s64 ax = (s16)g_dsp.r[sreg]; MOVSX(64, 16, RDX, MDisp(R11, sreg * 2)); // ax <<= 16; @@ -392,27 +400,18 @@ void DSPEmitter::addr(const UDSPInstruction opc) // s64 res = acc + ax; ADD(64, R(RAX), R(RDX)); // dsp_set_long_acc(dreg, res); - set_long_acc(dreg); // Update_SR_Register64(res, isCarry(acc, res), isOverflow(acc, ax, res)); - XOR(8, R(RSI), R(RSI)); - POP(64, R(RCX)); - CMP(64, R(RCX), R(RAX)); - - // Carry = (acc>res) - FixupBranch noCarry = J_CC(CC_G); - OR(8, R(RSI), Imm8(1)); - SetJumpTarget(noCarry); - - // Overflow = ((acc ^ res) & (ax ^ res)) < 0 - XOR(64, R(RCX), R(RAX)); - XOR(64, R(RDX), R(RAX)); - AND(64, R(RCX), R(RDX)); - CMP(64, R(RCX), Imm8(0)); - FixupBranch noOverflow = J_CC(CC_L); - OR(8, R(RSI), Imm8(2)); - SetJumpTarget(noOverflow); - - Update_SR_Register64(); + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + MOV(64, R(RSI), R(RAX)); + set_long_acc(dreg, RSI); + Update_SR_Register64_Carry(); + } + else + { + set_long_acc(dreg, RAX); + } + #else Default(opc); #endif @@ -423,61 +422,106 @@ void DSPEmitter::addr(const UDSPInstruction opc) // Adds secondary accumulator $axS to accumulator register $acD. // // flags out: x-xx xxxx -//void DSPEmitter::addax(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 8) & 0x1; -// u8 sreg = (opc >> 9) & 0x1; +void DSPEmitter::addax(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; // s64 acc = dsp_get_long_acc(dreg); + get_long_acc(dreg, RCX); + MOV(64, R(RAX), R(RCX)); // s64 ax = dsp_get_long_acx(sreg); + get_long_acx(sreg, RDX); // s64 res = acc + ax; - -// zeroWriteBackLog(); - + ADD(64, R(RAX), R(RDX)); // dsp_set_long_acc(dreg, res); // res = dsp_get_long_acc(dreg); // Update_SR_Register64(res, isCarry(acc, res), isOverflow(acc, ax, res)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + MOV(64, R(RSI), R(RAX)); + set_long_acc(dreg, RSI); + Update_SR_Register64_Carry(); + } + else + { + set_long_acc(dreg, RAX); + } +#else + Default(opc); +#endif +} // ADD $acD, $ac(1-D) // 0100 110d xxxx xxxx // Adds accumulator $ac(1-D) to accumulator register $acD. // // flags out: x-xx xxxx -//void DSPEmitter::add(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 8) & 0x1; +void DSPEmitter::add(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 8) & 0x1; // s64 acc0 = dsp_get_long_acc(dreg); + get_long_acc(dreg, RCX); + MOV(64, R(RAX), R(RCX)); // s64 acc1 = dsp_get_long_acc(1 - dreg); + get_long_acc(1 - dreg, RDX); // s64 res = acc0 + acc1; - -// zeroWriteBackLog(); - + ADD(64, R(RAX), R(RDX)); // dsp_set_long_acc(dreg, res); // res = dsp_get_long_acc(dreg); // Update_SR_Register64(res, isCarry(acc0, res), isOverflow(acc0, acc1, res)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + MOV(64, R(RSI), R(RAX)); + set_long_acc(dreg, RSI); + Update_SR_Register64_Carry(); + } + else + { + set_long_acc(dreg, RAX); + } +#else + Default(opc); +#endif +} // ADDP $acD // 0100 111d xxxx xxxx // Adds product register to accumulator register. // // flags out: x-xx xxxx -//void DSPEmitter::addp(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 8) & 0x1; +void DSPEmitter::addp(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 8) & 0x1; // s64 acc = dsp_get_long_acc(dreg); + get_long_acc(dreg, RCX); + MOV(64, R(RAX), R(RCX)); // s64 prod = dsp_get_long_prod(); + get_long_prod(RDX); // s64 res = acc + prod; - -// zeroWriteBackLog(); - + ADD(64, R(RAX), R(RDX)); // dsp_set_long_acc(dreg, res); // res = dsp_get_long_acc(dreg); // Update_SR_Register64(res, isCarry2(acc, res), isOverflow(acc, prod, res)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + MOV(64, R(RSI), R(RAX)); + set_long_acc(dreg, RSI); + Update_SR_Register64_Carry2(); + } + else + { + set_long_acc(dreg, RAX); + } +#else + Default(opc); +#endif +} // ADDAXL $acD, $axS.l // 0111 00sd xxxx xxxx @@ -508,77 +552,145 @@ void DSPEmitter::addr(const UDSPInstruction opc) // Adds immediate (16-bit sign extended) to mid accumulator $acD.hm. // // flags out: x-xx xxxx -//void DSPEmitter::addi(const UDSPInstruction opc) -//{ -// u8 areg = (opc >> 8) & 0x1; - +void DSPEmitter::addi(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 areg = (opc >> 8) & 0x1; // s64 acc = dsp_get_long_acc(areg); + get_long_acc(areg, RCX); + MOV(64, R(RAX), R(RCX)); // s64 imm = (s16)dsp_fetch_code(); -// imm <<= 16; + s16 imm = dsp_imem_read(compilePC+1); + //imm <<= 16; + MOV(16, R(RDX), Imm16(imm)); + MOVSX(64, 16, RDX, R(RDX)); + SHL(64, R(RDX), Imm8(16)); // s64 res = acc + imm; - + ADD(64, R(RAX), R(RDX)); // dsp_set_long_acc(areg, res); // res = dsp_get_long_acc(areg); // Update_SR_Register64(res, isCarry(acc, res), isOverflow(acc, imm, res)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + MOV(64, R(RSI), R(RAX)); + set_long_acc(areg, RSI); + Update_SR_Register64_Carry(); + } + else + { + set_long_acc(areg, RAX); + } +#else + Default(opc); +#endif +} // ADDIS $acD, #I // 0000 010d iiii iiii // Adds short immediate (8-bit sign extended) to mid accumulator $acD.hm. // // flags out: x-xx xxxx -//void DSPEmitter::addis(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 8) & 0x1; +void DSPEmitter::addis(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 8) & 0x1; // s64 acc = dsp_get_long_acc(dreg); + get_long_acc(dreg, RCX); + MOV(64, R(RAX), R(RCX)); // s64 imm = (s8)(u8)opc; // imm <<= 16; + MOV(8, R(RDX), Imm8((u8)opc)); + MOVSX(64, 8, RDX, R(RDX)); + SHL(64, R(RDX), Imm8(16)); // s64 res = acc + imm; - + ADD(64, R(RAX), R(RDX)); // dsp_set_long_acc(dreg, res); // res = dsp_get_long_acc(dreg); // Update_SR_Register64(res, isCarry(acc, res), isOverflow(acc, imm, res)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + MOV(64, R(RSI), R(RAX)); + set_long_acc(dreg, RSI); + Update_SR_Register64_Carry(); + } + else + { + set_long_acc(dreg, RAX); + } +#else + Default(opc); +#endif +} // INCM $acsD // 0111 010d xxxx xxxx // Increment 24-bit mid-accumulator $acsD. // // flags out: x-xx xxxx -//void DSPEmitter::incm(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 8) & 0x1; - -// s64 sub = 0x10000; +void DSPEmitter::incm(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 8) & 0x1; + s64 sub = 0x10000; // s64 acc = dsp_get_long_acc(dreg); + get_long_acc(dreg, RCX); + MOV(64, R(RAX), R(RCX)); // s64 res = acc + sub; - -// zeroWriteBackLog(); -// + ADD(64, R(RAX), Imm32((u32)sub)); // dsp_set_long_acc(dreg, res); // res = dsp_get_long_acc(dreg); // Update_SR_Register64(res, isCarry(acc, res), isOverflow(acc, sub, res)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + MOV(64, R(RDX), Imm32((u32)sub)); + MOV(64, R(RSI), R(RAX)); + set_long_acc(dreg, RSI); + Update_SR_Register64_Carry(); + } + else + { + set_long_acc(dreg); + Update_SR_Register64_Carry(); + } +#else + Default(opc); +#endif +} // INC $acD // 0111 011d xxxx xxxx // Increment accumulator $acD. // // flags out: x-xx xxxx -//void DSPEmitter::inc(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 8) & 0x1; - +void DSPEmitter::inc(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 8) & 0x1; // s64 acc = dsp_get_long_acc(dreg); -// s64 res = acc + 1; - -// zeroWriteBackLog(); - + get_long_acc(dreg, RCX); + MOV(64, R(RAX), R(RCX)); +// s64 res = acc + 1; + ADD(64, R(RAX), Imm8(1)); // dsp_set_long_acc(dreg, res); // res = dsp_get_long_acc(dreg); // Update_SR_Register64(res, isCarry(acc, res), isOverflow(acc, 1, res)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + MOV(64, R(RDX), Imm64(1)); + MOV(64, R(RSI), R(RAX)); + set_long_acc(dreg, RSI); + Update_SR_Register64_Carry(); + } + else + { + set_long_acc(dreg); + Update_SR_Register64_Carry(); + } +#else + Default(opc); +#endif +} //---- @@ -587,122 +699,216 @@ void DSPEmitter::addr(const UDSPInstruction opc) // Subtracts register $axS.L from accumulator $acD.M register. // // flags out: x-xx xxxx -//void DSPEmitter::subr(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 8) & 0x1; -// u8 sreg = ((opc >> 9) & 0x3) + DSP_REG_AXL0; +void DSPEmitter::subr(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 8) & 0x1; + u8 sreg = ((opc >> 9) & 0x3) + DSP_REG_AXL0; // s64 acc = dsp_get_long_acc(dreg); + get_long_acc(dreg, RCX); + MOV(64, R(RAX), R(RCX)); // s64 ax = (s16)g_dsp.r[sreg]; + MOV(64, R(R11), ImmPtr(&g_dsp.r)); + MOVSX(64, 16, RDX, MDisp(R11, sreg * 2)); // ax <<= 16; + SHL(64, R(RDX), Imm8(16)); // s64 res = acc - ax; - -// zeroWriteBackLog(); - + SUB(64, R(RAX), R(RDX)); // dsp_set_long_acc(dreg, res); // res = dsp_get_long_acc(dreg); // Update_SR_Register64(res, isCarry2(acc, res), isOverflow(acc, -ax, res)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + NEG(64, R(RDX)); + MOV(64, R(RSI), R(RAX)); + set_long_acc(dreg, RSI); + Update_SR_Register64_Carry2(); + } + else + { + set_long_acc(dreg, RAX); + } +#else + Default(opc); +#endif +} // SUBAX $acD, $axS // 0101 10sd xxxx xxxx // Subtracts secondary accumulator $axS from accumulator register $acD. // // flags out: x-xx xxxx -//void DSPEmitter::subax(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 8) & 0x1; -// u8 sreg = (opc >> 9) & 0x1; +void DSPEmitter::subax(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; // s64 acc = dsp_get_long_acc(dreg); + get_long_acc(dreg, RCX); + MOV(64, R(RAX), R(RCX)); // s64 acx = dsp_get_long_acx(sreg); + get_long_acx(sreg, RDX); // s64 res = acc - acx; - -// zeroWriteBackLog(); - + SUB(64, R(RAX), R(RDX)); // dsp_set_long_acc(dreg, res); // res = dsp_get_long_acc(dreg); // Update_SR_Register64(res, isCarry2(acc, res), isOverflow(acc, -acx, res)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + NEG(64, R(RDX)); + MOV(64, R(RSI), R(RAX)); + set_long_acc(dreg, RSI); + Update_SR_Register64_Carry2(); + } + else + { + set_long_acc(dreg, RAX); + } +#else + Default(opc); +#endif +} // SUB $acD, $ac(1-D) // 0101 110d xxxx xxxx // Subtracts accumulator $ac(1-D) from accumulator register $acD. // // flags out: x-xx xxxx -//void DSPEmitter::sub(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 8) & 0x1; - +void DSPEmitter::sub(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 8) & 0x1; // s64 acc1 = dsp_get_long_acc(dreg); + get_long_acc(dreg, RCX); + MOV(64, R(RAX), R(RCX)); // s64 acc2 = dsp_get_long_acc(1 - dreg); + get_long_acc(1 - dreg, RDX); // s64 res = acc1 - acc2; - -// zeroWriteBackLog(); - + SUB(64, R(RAX), R(RDX)); // dsp_set_long_acc(dreg, res); // res = dsp_get_long_acc(dreg); // Update_SR_Register64(res, isCarry2(acc1, res), isOverflow(acc1, -acc2, res)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + NEG(64, R(RDX)); + MOV(64, R(RSI), R(RAX)); + set_long_acc(dreg, RSI); + Update_SR_Register64_Carry2(); + } + else + { + set_long_acc(dreg, RAX); + } +#else + Default(opc); +#endif +} // SUBP $acD // 0101 111d xxxx xxxx // Subtracts product register from accumulator register. // // flags out: x-xx xxxx -//void DSPEmitter::subp(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 8) & 0x1; - +void DSPEmitter::subp(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 8) & 0x1; // s64 acc = dsp_get_long_acc(dreg); + get_long_acc(dreg, RCX); + MOV(64, R(RAX), R(RCX)); // s64 prod = dsp_get_long_prod(); + get_long_prod(RDX); // s64 res = acc - prod; - -// zeroWriteBackLog(); - + SUB(64, R(RAX), R(RDX)); // dsp_set_long_acc(dreg, res); // res = dsp_get_long_acc(dreg); // Update_SR_Register64(res, isCarry2(acc, res), isOverflow(acc, -prod, res)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + NEG(64, R(RDX)); + MOV(64, R(RSI), R(RAX)); + set_long_acc(dreg, RSI); + Update_SR_Register64_Carry2(); + } + else + { + set_long_acc(dreg, RAX); + } +#else + Default(opc); +#endif +} // DECM $acsD // 0111 100d xxxx xxxx // Decrement 24-bit mid-accumulator $acsD. // // flags out: x-xx xxxx -//void DSPEmitter::decm(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 8) & 0x01; - -// s64 sub = 0x10000; +void DSPEmitter::decm(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 8) & 0x01; + s64 sub = 0x10000; // s64 acc = dsp_get_long_acc(dreg); + get_long_acc(dreg, RCX); + MOV(64, R(RAX), R(RCX)); // s64 res = acc - sub; - -// zeroWriteBackLog(); -// + SUB(64, R(RAX), Imm32((u32)sub)); // dsp_set_long_acc(dreg, res); // res = dsp_get_long_acc(dreg); // Update_SR_Register64(res, isCarry2(acc, res), isOverflow(acc, -sub, res)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + MOV(64, R(RDX), Imm64(-sub)); + MOV(64, R(RSI), R(RAX)); + set_long_acc(dreg, RSI); + Update_SR_Register64_Carry2(); + } + else + { + set_long_acc(dreg, RAX); + } +#else + Default(opc); +#endif +} // DEC $acD // 0111 101d xxxx xxxx // Decrement accumulator $acD. // // flags out: x-xx xxxx -//void DSPEmitter::dec(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 8) & 0x01; - +void DSPEmitter::dec(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 8) & 0x01; // s64 acc = dsp_get_long_acc(dreg); + get_long_acc(dreg, RCX); + MOV(64, R(RAX), R(RCX)); // s64 res = acc - 1; - -// zeroWriteBackLog(); - + SUB(64, R(RAX), Imm8(1)); // dsp_set_long_acc(dreg, res); + set_long_acc(dreg); // res = dsp_get_long_acc(dreg); // Update_SR_Register64(res, isCarry2(acc, res), isOverflow(acc, -1, res)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + MOV(8, R(RDX), Imm8(1)); + NEG(8, R(RDX)); + MOV(64, R(RSI), R(RAX)); + set_long_acc(dreg, RSI); + Update_SR_Register64_Carry2(); + } + else + { + set_long_acc(dreg, RAX); + } +#else + Default(opc); +#endif +} //---- @@ -711,38 +917,55 @@ void DSPEmitter::addr(const UDSPInstruction opc) // Negate accumulator $acD. // // flags out: --xx xx00 -//void DSPEmitter::neg(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 8) & 0x1; -// +void DSPEmitter::neg(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 8) & 0x1; // s64 acc = dsp_get_long_acc(dreg); + get_long_acc(dreg); // acc = 0 - acc; - -// zeroWriteBackLog(); - + NEG(64, R(RAX)); // dsp_set_long_acc(dreg, acc); + set_long_acc(dreg); // Update_SR_Register64(dsp_get_long_acc(dreg)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } +#else + Default(opc); +#endif +} // ABS $acD // 1010 d001 xxxx xxxx // absolute value of $acD // // flags out: --xx xx00 -//void DSPEmitter::abs(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 11) & 0x1; +void DSPEmitter::abs(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 11) & 0x1; // s64 acc = dsp_get_long_acc(dreg); - -// if (acc < 0) -// acc = 0 - acc; -// -// zeroWriteBackLog(); - + get_long_acc(dreg); +// if (acc < 0) acc = 0 - acc; + CMP(64, R(RAX), Imm8(0)); + FixupBranch lessThan = J_CC(CC_L); + NEG(64, R(RAX)); + set_long_acc(dreg); + SetJumpTarget(lessThan); // dsp_set_long_acc(dreg, acc); + set_long_acc(dreg); // Update_SR_Register64(dsp_get_long_acc(dreg)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } +#else + Default(opc); +#endif +} //---- // MOVR $acD, $axS.R @@ -752,54 +975,76 @@ void DSPEmitter::addr(const UDSPInstruction opc) // TODO: Check what happens to acD.h. // // flags out: --xx xx00 -//void DSPEmitter::movr(const UDSPInstruction opc) -//{ -// u8 areg = (opc >> 8) & 0x1; -// u8 sreg = ((opc >> 9) & 0x3) + DSP_REG_AXL0; -// +void DSPEmitter::movr(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 areg = (opc >> 8) & 0x1; + u8 sreg = ((opc >> 9) & 0x3) + DSP_REG_AXL0; + // s64 acc = (s16)g_dsp.r[sreg]; + MOV(64, R(R11), ImmPtr(&g_dsp.r)); + MOVSX(64, 16, RAX, MDisp(R11, sreg * 2)); // acc <<= 16; + SHL(64, R(RAX), Imm8(16)); // acc &= ~0xffff; - -// zeroWriteBackLog(); - // dsp_set_long_acc(areg, acc); -// Update_SR_Register64(acc); -//} + set_long_acc(areg); + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } +#else + Default(opc); +#endif +} // MOVAX $acD, $axS // 0110 10sd xxxx xxxx // Moves secondary accumulator $axS to accumulator $axD. // // flags out: --xx xx00 -//void DSPEmitter::movax(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 8) & 0x1; -// u8 sreg = (opc >> 9) & 0x1; +void DSPEmitter::movax(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; // s64 acx = dsp_get_long_acx(sreg); - -// zeroWriteBackLog(); - + get_long_acx(sreg); // dsp_set_long_acc(dreg, acx); + set_long_acc(dreg); // Update_SR_Register64(acx); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } +#else + Default(opc); +#endif +} // MOV $acD, $ac(1-D) // 0110 110d xxxx xxxx // Moves accumulator $ax(1-D) to accumulator $axD. // // flags out: --x0 xx00 -//void DSPEmitter::mov(const UDSPInstruction opc) -//{ -// u8 dreg = (opc >> 8) & 0x1; +void DSPEmitter::mov(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 dreg = (opc >> 8) & 0x1; // u64 acc = dsp_get_long_acc(1 - dreg); - -// zeroWriteBackLog(); - + get_long_acc(1 - dreg); // dsp_set_long_acc(dreg, acc); + set_long_acc(dreg); // Update_SR_Register64(acc); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } +#else + Default(opc); +#endif +} //---- @@ -810,6 +1055,7 @@ void DSPEmitter::addr(const UDSPInstruction opc) // flags out: --xx xx00 void DSPEmitter::lsl16(const UDSPInstruction opc) { + Default(opc); return; // TODO: Breaks ZTP Wii #ifdef _M_X64 u8 areg = (opc >> 8) & 0x1; // s64 acc = dsp_get_long_acc(areg); @@ -819,7 +1065,10 @@ void DSPEmitter::lsl16(const UDSPInstruction opc) // dsp_set_long_acc(areg, acc); set_long_acc(areg); // Update_SR_Register64(dsp_get_long_acc(areg)); - Update_SR_Register64(); + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } #else Default(opc); #endif @@ -830,37 +1079,54 @@ void DSPEmitter::lsl16(const UDSPInstruction opc) // Logically shifts right accumulator $acR by 16. // // flags out: --xx xx00 -//void DSPEmitter::lsr16(const UDSPInstruction opc) -//{ -// u8 areg = (opc >> 8) & 0x1; +void DSPEmitter::lsr16(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 areg = (opc >> 8) & 0x1; // u64 acc = dsp_get_long_acc(areg); + get_long_acc(areg); // acc &= 0x000000FFFFFFFFFFULL; // Lop off the extraneous sign extension our 64-bit fake accum causes // acc >>= 16; - -// zeroWriteBackLog(); - + SHR(64, R(RAX), Imm8(16)); + AND(64, R(RAX), Imm32(0xffffff)); // dsp_set_long_acc(areg, (s64)acc); + set_long_acc(areg); // Update_SR_Register64(dsp_get_long_acc(areg)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } +#else + Default(opc); +#endif +} // ASR16 $acR // 1001 r001 xxxx xxxx // Arithmetically shifts right accumulator $acR by 16. // // flags out: --xx xx00 -//void DSPEmitter::asr16(const UDSPInstruction opc) -//{ -// u8 areg = (opc >> 11) & 0x1; +void DSPEmitter::asr16(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 areg = (opc >> 11) & 0x1; // s64 acc = dsp_get_long_acc(areg); + get_long_acc(areg); // acc >>= 16; - -// zeroWriteBackLog(); - + SHR(64, R(RAX), Imm8(16)); // dsp_set_long_acc(areg, acc); + set_long_acc(areg); // Update_SR_Register64(dsp_get_long_acc(areg)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } +#else + Default(opc); +#endif +} // LSL $acR, #I // 0001 010r 00ii iiii @@ -876,12 +1142,15 @@ void DSPEmitter::lsl(const UDSPInstruction opc) get_long_acc(rreg); // acc <<= shift; - SHL(64, R(RAX), Imm8(shift)); + SHL(64, R(RAX), Imm8((u8)shift)); // dsp_set_long_acc(rreg, acc); set_long_acc(rreg); // Update_SR_Register64(dsp_get_long_acc(rreg)); - Update_SR_Register64(); + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } #else Default(opc); #endif @@ -916,17 +1185,26 @@ void DSPEmitter::lsl(const UDSPInstruction opc) // Logically shifts left accumulator $acR by number specified by value I. // // flags out: --xx xx00 -//void DSPEmitter::asl(const UDSPInstruction opc) -//{ -// u8 rreg = (opc >> 8) & 0x01; -// u16 shift = opc & 0x3f; +void DSPEmitter::asl(const UDSPInstruction opc) +{ +#ifdef _M_X64 + u8 rreg = (opc >> 8) & 0x01; + u16 shift = opc & 0x3f; // u64 acc = dsp_get_long_acc(rreg); - + get_long_acc(rreg); // acc <<= shift; -// + SHL(64, R(RAX), Imm8((u8)shift)); // dsp_set_long_acc(rreg, acc); + set_long_acc(rreg); // Update_SR_Register64(dsp_get_long_acc(rreg)); -//} + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } +#else + Default(opc); +#endif +} // ASR $acR, #I // 0001 010r 11ii iiii diff --git a/Source/Core/DSPCore/Src/Jit/DSPJitCCUtil.cpp b/Source/Core/DSPCore/Src/Jit/DSPJitCCUtil.cpp index d0e0e9b7d8..6826c87820 100644 --- a/Source/Core/DSPCore/Src/Jit/DSPJitCCUtil.cpp +++ b/Source/Core/DSPCore/Src/Jit/DSPJitCCUtil.cpp @@ -29,62 +29,124 @@ using namespace Gen; // In: RAX: s64 _Value // In: RCX: 1 = carry, 2 = overflow // Clobbers RDX -void DSPEmitter::Update_SR_Register64(bool carry, bool overflow) +void DSPEmitter::Update_SR_Register(Gen::X64Reg val) +{ +#ifdef _M_X64 + // // 0x04 + // if (_Value == 0) g_dsp.r[DSP_REG_SR] |= SR_ARITH_ZERO; + CMP(64, R(val), Imm8(0)); + FixupBranch notZero = J_CC(CC_NZ); + OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_ARITH_ZERO)); + SetJumpTarget(notZero); + + // // 0x08 + // if (_Value < 0) g_dsp.r[DSP_REG_SR] |= SR_SIGN; + CMP(64, R(val), Imm8(0)); + FixupBranch greaterThanEqual = J_CC(CC_GE); + OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_SIGN)); + SetJumpTarget(greaterThanEqual); + + // // 0x10 + // if (_Value != (s32)_Value) g_dsp.r[DSP_REG_SR] |= SR_OVER_S32; + MOVSX(64, 32, RDX, R(val)); + CMP(64, R(RDX), R(val)); + FixupBranch noOverS32 = J_CC(CC_E); + OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_OVER_S32)); + SetJumpTarget(noOverS32); + + // // 0x20 - Checks if top bits of m are equal + // if (((_Value & 0xc0000000) == 0) || ((_Value & 0xc0000000) == 0xc0000000)) + AND(32, R(val), Imm32(0xc0000000)); + CMP(32, R(val), Imm32(0)); + FixupBranch zeroC = J_CC(CC_E); + CMP(32, R(val), Imm32(0xc0000000)); + FixupBranch cC = J_CC(CC_NE); + SetJumpTarget(zeroC); + // g_dsp.r[DSP_REG_SR] |= SR_TOP2BITS; + OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_TOP2BITS)); + SetJumpTarget(cC); +#endif +} + +// In: RAX: s64 _Value +// In: RCX: 1 = carry, 2 = overflow +// Clobbers RDX +void DSPEmitter::Update_SR_Register64(Gen::X64Reg val) { #ifdef _M_X64 // g_dsp.r[DSP_REG_SR] &= ~SR_CMP_MASK; AND(16, MDisp(R11, DSP_REG_SR * 2), Imm16(~SR_CMP_MASK)); + Update_SR_Register(val); +#endif +} + +// In: RAX: s64 _Value +// In: RCX: 1 = carry, 2 = overflow +// Clobbers RDX +void DSPEmitter::Update_SR_Register64_Carry(Gen::X64Reg val) +{ +#ifdef _M_X64 + // g_dsp.r[DSP_REG_SR] &= ~SR_CMP_MASK; + AND(16, MDisp(R11, DSP_REG_SR * 2), Imm16(~SR_CMP_MASK)); + + CMP(64, R(RCX), R(val)); // 0x01 // g_dsp.r[DSP_REG_SR] |= SR_CARRY; - TEST(8, R(RSI), Imm8(1)); - FixupBranch noCarry = J_CC(CC_NZ); + // Carry = (acc>res) + FixupBranch noCarry = J_CC(CC_BE); OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_CARRY)); SetJumpTarget(noCarry); // 0x02 and 0x80 // g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW; // g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW_STICKY; - TEST(8, R(RSI), Imm8(2)); - FixupBranch noOverflow = J_CC(CC_NZ); + // Overflow = ((acc ^ res) & (ax ^ res)) < 0 + XOR(64, R(RCX), R(val)); + XOR(64, R(RDX), R(val)); + AND(64, R(RCX), R(RDX)); + CMP(64, R(RCX), Imm8(0)); + FixupBranch noOverflow = J_CC(CC_GE); OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_OVERFLOW | SR_OVERFLOW_STICKY)); SetJumpTarget(noOverflow); -// // 0x04 -// if (_Value == 0) g_dsp.r[DSP_REG_SR] |= SR_ARITH_ZERO; - TEST(64, R(RAX), R(RAX)); - FixupBranch notZero = J_CC(CC_NZ); - OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_ARITH_ZERO)); - SetJumpTarget(notZero); - -// // 0x08 -// if (_Value < 0) g_dsp.r[DSP_REG_SR] |= SR_SIGN; - FixupBranch greaterThanEqual = J_CC(CC_NS); - OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_SIGN)); - SetJumpTarget(greaterThanEqual); - -// // 0x10 -// if (_Value != (s32)_Value) g_dsp.r[DSP_REG_SR] |= SR_OVER_S32; - MOVSX(64, 32, RDX, R(RAX)); - CMP(64, R(RDX), R(RAX)); - FixupBranch noOverS32 = J_CC(CC_E); - OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_OVER_S32)); - SetJumpTarget(noOverS32); - -// // 0x20 - Checks if top bits of m are equal -// if (((_Value & 0xc0000000) == 0) || ((_Value & 0xc0000000) == 0xc0000000)) - AND(32, R(EAX), Imm32(0xc0000000)); - CMP(32, R(EAX), Imm32(0)); - FixupBranch zeroC = J_CC(CC_E); - CMP(32, R(EAX), Imm32(0xc0000000)); - FixupBranch cC = J_CC(CC_NE); - SetJumpTarget(zeroC); -// g_dsp.r[DSP_REG_SR] |= SR_TOP2BITS; - OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_TOP2BITS)); - SetJumpTarget(cC); + Update_SR_Register(val); #endif } +// In: RAX: s64 _Value +// In: RCX: 1 = carry, 2 = overflow +// Clobbers RDX +void DSPEmitter::Update_SR_Register64_Carry2(Gen::X64Reg val) +{ +#ifdef _M_X64 + // g_dsp.r[DSP_REG_SR] &= ~SR_CMP_MASK; + AND(16, MDisp(R11, DSP_REG_SR * 2), Imm16(~SR_CMP_MASK)); + + CMP(64, R(RCX), R(val)); + + // 0x01 + // g_dsp.r[DSP_REG_SR] |= SR_CARRY; + // Carry2 = (acc>=res) + FixupBranch noCarry2 = J_CC(CC_B); + OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_CARRY)); + SetJumpTarget(noCarry2); + + // 0x02 and 0x80 + // g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW; + // g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW_STICKY; + // Overflow = ((acc ^ res) & (ax ^ res)) < 0 + XOR(64, R(RCX), R(val)); + XOR(64, R(RDX), R(val)); + AND(64, R(RCX), R(RDX)); + CMP(64, R(RCX), Imm8(0)); + FixupBranch noOverflow = J_CC(CC_GE); + OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_OVERFLOW | SR_OVERFLOW_STICKY)); + SetJumpTarget(noOverflow); + + Update_SR_Register(); +#endif +} //void DSPEmitter::Update_SR_Register16(s16 _Value, bool carry, bool overflow, bool overS32) //{ diff --git a/Source/Core/DSPCore/Src/Jit/DSPJitLoadStore.cpp b/Source/Core/DSPCore/Src/Jit/DSPJitLoadStore.cpp index a488cd2a1d..fdd5fc09a6 100644 --- a/Source/Core/DSPCore/Src/Jit/DSPJitLoadStore.cpp +++ b/Source/Core/DSPCore/Src/Jit/DSPJitLoadStore.cpp @@ -319,7 +319,7 @@ void DSPEmitter::ilrrd(const UDSPInstruction opc) MOV(16, MDisp(R11,dreg*2), R(RAX)); #endif dsp_conditional_extend_accum(dreg); - dsp_decrement_addr_reg(reg); + decrement_addr_reg(reg); } // ILRRI $acD.m, @$S @@ -345,7 +345,7 @@ void DSPEmitter::ilrri(const UDSPInstruction opc) MOV(16, MDisp(R11,dreg*2), R(RAX)); #endif dsp_conditional_extend_accum(dreg); - dsp_increment_addr_reg(reg); + increment_addr_reg(reg); } // ILRRN $acD.m, @$arS diff --git a/Source/Core/DSPCore/Src/Jit/DSPJitMultiplier.cpp b/Source/Core/DSPCore/Src/Jit/DSPJitMultiplier.cpp index 3dc6f7ff62..d8f4d59aa5 100644 --- a/Source/Core/DSPCore/Src/Jit/DSPJitMultiplier.cpp +++ b/Source/Core/DSPCore/Src/Jit/DSPJitMultiplier.cpp @@ -22,6 +22,7 @@ #include "../DSPIntUtil.h" #include "../DSPEmitter.h" +#include "../DSPAnalyzer.h" #include "x64Emitter.h" #include "ABI.h" using namespace Gen; @@ -166,10 +167,13 @@ void DSPEmitter::clrp(const UDSPInstruction opc) void DSPEmitter::tstprod(const UDSPInstruction opc) { #ifdef _M_X64 -// s64 prod = dsp_get_long_prod(); - get_long_prod(); -// Update_SR_Register64(prod); - Update_SR_Register64(); + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { +// s64 prod = dsp_get_long_prod(); + get_long_prod(); +// Update_SR_Register64(prod); + Update_SR_Register64(); + } #else Default(opc); #endif @@ -192,7 +196,10 @@ void DSPEmitter::movp(const UDSPInstruction opc) // dsp_set_long_acc(dreg, acc); set_long_acc(dreg); // Update_SR_Register64(acc); - Update_SR_Register64(); + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } #else Default(opc); #endif @@ -215,7 +222,10 @@ void DSPEmitter::movnp(const UDSPInstruction opc) // dsp_set_long_acc(dreg, acc); set_long_acc(dreg); // Update_SR_Register64(acc); - Update_SR_Register64(); + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } #else Default(opc); #endif @@ -237,7 +247,10 @@ void DSPEmitter::movpz(const UDSPInstruction opc) // dsp_set_long_acc(dreg, acc); set_long_acc(dreg); // Update_SR_Register64(acc); - Update_SR_Register64(); + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } #else Default(opc); #endif @@ -342,7 +355,10 @@ void DSPEmitter::mulac(const UDSPInstruction opc) POP(64, R(RAX)); set_long_acc(rreg); // Update_SR_Register64(dsp_get_long_acc(rreg)); - Update_SR_Register64(); + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } #else Default(opc); #endif @@ -368,7 +384,10 @@ void DSPEmitter::mulmv(const UDSPInstruction opc) POP(64, R(RAX)); set_long_acc(rreg); // Update_SR_Register64(dsp_get_long_acc(rreg)); - Update_SR_Register64(); + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } #else Default(opc); #endif @@ -395,7 +414,10 @@ void DSPEmitter::mulmvz(const UDSPInstruction opc) POP(64, R(RAX)); set_long_acc(rreg); // Update_SR_Register64(dsp_get_long_acc(rreg)); - Update_SR_Register64(); + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } #else Default(opc); #endif @@ -555,7 +577,10 @@ void DSPEmitter::mulcac(const UDSPInstruction opc) POP(64, R(RAX)); set_long_acc(rreg); // Update_SR_Register64(dsp_get_long_acc(rreg)); - Update_SR_Register64(); + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } #else Default(opc); #endif @@ -591,7 +616,10 @@ void DSPEmitter::mulcmv(const UDSPInstruction opc) POP(64, R(RAX)); set_long_acc(rreg); // Update_SR_Register64(dsp_get_long_acc(rreg)); - Update_SR_Register64(); + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } #else Default(opc); #endif @@ -629,7 +657,10 @@ void DSPEmitter::mulcmvz(const UDSPInstruction opc) POP(64, R(RAX)); set_long_acc(rreg); // Update_SR_Register64(dsp_get_long_acc(rreg)); - Update_SR_Register64(); + if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR)) + { + Update_SR_Register64(); + } #else Default(opc); #endif diff --git a/Source/Core/DSPCore/Src/Jit/DSPJitUtil.cpp b/Source/Core/DSPCore/Src/Jit/DSPJitUtil.cpp index 08b3ea5062..814de5786c 100644 --- a/Source/Core/DSPCore/Src/Jit/DSPJitUtil.cpp +++ b/Source/Core/DSPCore/Src/Jit/DSPJitUtil.cpp @@ -466,14 +466,15 @@ void DSPEmitter::dmem_read_imm(u16 address) // Returns s64 in RAX // Clobbers RSI, RDI -void DSPEmitter::get_long_prod() +void DSPEmitter::get_long_prod(X64Reg long_prod) { #ifdef _M_X64 + /* MOV(64, R(R11), ImmPtr(&g_dsp.r)); //s64 val = (s8)(u8)g_dsp.r[DSP_REG_PRODH]; - MOVSX(64, 8, RAX, MDisp(R11,DSP_REG_PRODH*2)); + MOVSX(64, 8, long_prod, MDisp(R11,DSP_REG_PRODH*2)); //val <<= 32; - SHL(64, R(RAX), Imm8(32)); + SHL(64, R(long_prod), Imm8(32)); //s64 low_prod = g_dsp.r[DSP_REG_PRODM]; MOVSX(64, 16, RSI, MDisp(R11,DSP_REG_PRODM*2)); //low_prod += g_dsp.r[DSP_REG_PRODM2]; @@ -481,33 +482,50 @@ void DSPEmitter::get_long_prod() ADD(16, R(RSI), R(EDI)); //low_prod <<= 16; SHL(64, R(RSI), Imm8(16)); - OR(64, R(RAX), R(RSI)); + OR(64, R(long_prod), R(RSI)); //low_prod |= g_dsp.r[DSP_REG_PRODL]; - MOV(16, R(RAX), MDisp(R11,DSP_REG_PRODL*2)); + MOV(16, R(long_prod), MDisp(R11,DSP_REG_PRODL*2)); //return val; + */ + + MOV(64, R(R11), ImmPtr(&g_dsp.r)); + //s64 val = (s8)(u8)g_dsp.r[DSP_REG_PRODH]; + MOVSX(64, 8, long_prod, MDisp(R11,DSP_REG_PRODH*2)); + //val <<= 32; + SHL(64, R(long_prod), Imm8(16)); + //s64 low_prod = g_dsp.r[DSP_REG_PRODM]; + OR(16, R(long_prod), MDisp(R11,DSP_REG_PRODM*2)); + //low_prod += g_dsp.r[DSP_REG_PRODM2]; + ADD(16, R(long_prod), MDisp(R11,DSP_REG_PRODM2*2)); + //low_prod <<= 16; + SHL(64, R(long_prod), Imm8(16)); + //low_prod |= g_dsp.r[DSP_REG_PRODL]; + OR(16, R(long_prod), MDisp(R11,DSP_REG_PRODL*2)); + //return val; + #endif } // Returns s64 in RAX // Clobbers RSI -void DSPEmitter::get_long_prod_round_prodl() +void DSPEmitter::get_long_prod_round_prodl(X64Reg long_prod) { #ifdef _M_X64 //s64 prod = dsp_get_long_prod(); get_long_prod(); //if (prod & 0x10000) prod = (prod + 0x8000) & ~0xffff; - TEST(32, R(EAX), Imm32(0x10000)); + TEST(32, R(long_prod), Imm32(0x10000)); FixupBranch jump = J_CC(CC_Z); - ADD(64, R(RAX), Imm32(0x8000)); + ADD(64, R(long_prod), Imm32(0x8000)); MOV(64, R(ESI), Imm64(~0xffff)); - AND(64, R(RAX), R(RSI)); + AND(64, R(long_prod), R(RSI)); FixupBranch ret = J(); //else prod = (prod + 0x7fff) & ~0xffff; SetJumpTarget(jump); - ADD(64, R(RAX), Imm32(0x7fff)); + ADD(64, R(long_prod), Imm32(0x7fff)); MOV(64, R(RSI), Imm64(~0xffff)); - AND(64, R(RAX), R(RSI)); + AND(64, R(long_prod), R(RSI)); SetJumpTarget(ret); //return prod; #endif @@ -523,13 +541,13 @@ void DSPEmitter::set_long_prod() MOV(64, R(R11), ImmPtr(&g_dsp.r)); MOV(16, MDisp(R11, DSP_REG_PRODL * 2), R(AX)); // val >>= 16; - SHR(64, R(RAX), Imm8(16)); + SAR(64, R(RAX), Imm8(16)); // g_dsp.r[DSP_REG_PRODM] = (u16)val; MOV(16, MDisp(R11, DSP_REG_PRODM * 2), R(AX)); // val >>= 16; - SHR(64, R(RAX), Imm8(16)); + SAR(64, R(RAX), Imm8(16)); // g_dsp.r[DSP_REG_PRODH] = (u8)val; - MOVZX(64, 8, RAX, R(AL)); + MOVSX(64, 8, RAX, R(AL)); MOV(8, MDisp(R11, DSP_REG_PRODH * 2), R(AL)); // g_dsp.r[DSP_REG_PRODM2] = 0; MOV(16, MDisp(R11, DSP_REG_PRODM2 * 2), Imm16(0)); @@ -537,40 +555,38 @@ void DSPEmitter::set_long_prod() } // Returns s64 in RAX -// Clobbers ESI -void DSPEmitter::get_long_acc(int _reg) +void DSPEmitter::get_long_acc(int _reg, X64Reg acc) { #ifdef _M_X64 // s64 high = (s64)(s8)g_dsp.r[DSP_REG_ACH0 + reg] << 32; MOV(64, R(R11), ImmPtr(&g_dsp.r)); - MOVSX(64, 8, EAX, MDisp(R11, (DSP_REG_ACH0 + _reg) * 2)); - SHL(64, R(EAX), Imm8(32)); + MOVSX(64, 8, acc, MDisp(R11, (DSP_REG_ACH0 + _reg) * 2)); + SHL(64, R(acc), Imm8(16)); // u32 mid_low = ((u32)g_dsp.r[DSP_REG_ACM0 + reg] << 16) | g_dsp.r[DSP_REG_ACL0 + reg]; - MOVZX(64, 16, RSI, MDisp(R11, (DSP_REG_ACM0 + _reg) * 2)); - SHL(32, R(RSI), Imm8(16)); - OR(64, R(EAX), R(RSI)); - MOVZX(64, 16, RSI, MDisp(R11, (DSP_REG_ACL0 + _reg) * 2)); - OR(64, R(EAX), R(RSI)); + OR(16, R(acc), MDisp(R11, (DSP_REG_ACM0 + _reg) * 2)); + SHL(64, R(acc), Imm8(16)); + OR(16, R(acc), MDisp(R11, (DSP_REG_ACL0 + _reg) * 2)); // return high | mid_low; #endif } // In: RAX = s64 val -void DSPEmitter::set_long_acc(int _reg) +// Clobbers the input reg +void DSPEmitter::set_long_acc(int _reg, X64Reg acc) { #ifdef _M_X64 // g_dsp.r[DSP_REG_ACL0 + _reg] = (u16)val; MOV(64, R(R11), ImmPtr(&g_dsp.r)); - MOV(16, MDisp(R11, (DSP_REG_ACL0 + _reg) * 2), R(AX)); + MOV(16, MDisp(R11, (DSP_REG_ACL0 + _reg) * 2), R(acc)); // val >>= 16; - SHR(64, R(RAX), Imm8(16)); + SHR(64, R(acc), Imm8(16)); // g_dsp.r[DSP_REG_ACM0 + _reg] = (u16)val; - MOV(16, MDisp(R11, (DSP_REG_ACM0 + _reg) * 2), R(AX)); + MOV(16, MDisp(R11, (DSP_REG_ACM0 + _reg) * 2), R(acc)); // val >>= 16; - SHR(64, R(RAX), Imm8(16)); + SHR(64, R(acc), Imm8(16)); // g_dsp.r[DSP_REG_ACH0 + _reg] = (u16)(s16)(s8)(u8)val; - MOVSX(16, 8, AX, R(AX)); - MOV(16, MDisp(R11, (DSP_REG_ACH0 + _reg) * 2), R(AX)); + MOVSX(64, 8, acc, R(acc)); + MOV(16, MDisp(R11, (DSP_REG_ACH0 + _reg) * 2), R(acc)); #endif } @@ -584,6 +600,18 @@ void DSPEmitter::get_acc_m(int _reg) #endif } +// Returns u32 in EAX +void DSPEmitter::get_long_acx(int _reg, X64Reg acx) +{ +// return ((u32)g_dsp.r[DSP_REG_AXH0 + _reg] << 16) | g_dsp.r[DSP_REG_AXL0 + _reg]; +#ifdef _M_X64 + MOV(64, R(R11), ImmPtr(&g_dsp.r)); + MOVSX(64, 16, acx, MDisp(R11, (DSP_REG_AXH0 + _reg) * 2)); + SHL(64, R(acx), Imm8(16)); + OR(16, R(acx), MDisp(R11, (DSP_REG_AXL0 + _reg) * 2)); +#endif +} + // Returns s16 in EAX void DSPEmitter::get_ax_l(int _reg) {