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JitArm64: Change parameter order for quantized load routines 

EmitBackpatchRoutine (see the upcoming commits) expects
the address to be in W0 for loads and W1 for stores.
This commit is contained in:
JosJuice 2021-07-08 18:20:38 +02:00
parent 36b3d51523
commit 6c3141e0cc
3 changed files with 28 additions and 16 deletions
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3
Source/Core/Core/PowerPC/JitArm64/Jit.h
View File

@ -253,7 +253,8 @@ protected:
void GenerateConvertDoubleToSingle(); void GenerateConvertDoubleToSingle();
void GenerateConvertSingleToDouble(); void GenerateConvertSingleToDouble();
void GenerateFPRF(bool single); void GenerateFPRF(bool single);
void GenerateQuantizedLoadStores(); void GenerateQuantizedLoads();
void GenerateQuantizedStores();
// Profiling // Profiling
void BeginTimeProfile(JitBlock* b); void BeginTimeProfile(JitBlock* b);

8
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
View File

@ -25,8 +25,8 @@ void JitArm64::psq_lXX(UGeckoInstruction inst)
FALLBACK_IF(!MSR.DR); FALLBACK_IF(!MSR.DR);
// X30 is LR // X30 is LR
// X0 contains the scale // X0 is the address
// X1 is the address // X1 contains the scale
// X2 is a temporary // X2 is a temporary
// Q0 is the return register // Q0 is the return register
// Q1 is a temporary // Q1 is a temporary
@ -39,8 +39,8 @@ void JitArm64::psq_lXX(UGeckoInstruction inst)
gpr.Lock(ARM64Reg::W0, ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W30); gpr.Lock(ARM64Reg::W0, ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W30);
fpr.Lock(ARM64Reg::Q0, ARM64Reg::Q1); fpr.Lock(ARM64Reg::Q0, ARM64Reg::Q1);
constexpr ARM64Reg scale_reg = ARM64Reg::W0; constexpr ARM64Reg addr_reg = ARM64Reg::W0;
constexpr ARM64Reg addr_reg = ARM64Reg::W1; constexpr ARM64Reg scale_reg = ARM64Reg::W1;
constexpr ARM64Reg type_reg = ARM64Reg::W2; constexpr ARM64Reg type_reg = ARM64Reg::W2;
ARM64Reg VS; ARM64Reg VS;

33
Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
View File

@ -223,7 +223,8 @@ void JitArm64::GenerateCommonAsm()
GenerateFPRF(false); GenerateFPRF(false);
JitRegister::Register(GetAsmRoutines()->fprf_single, GetCodePtr(), "JIT_FPRF"); JitRegister::Register(GetAsmRoutines()->fprf_single, GetCodePtr(), "JIT_FPRF");
GenerateQuantizedLoadStores(); GenerateQuantizedLoads();
GenerateQuantizedStores();
} }
// Input: X1 contains input, and D0 contains result of running the input through AArch64 FRECPE. // Input: X1 contains input, and D0 contains result of running the input through AArch64 FRECPE.
@ -483,17 +484,15 @@ void JitArm64::GenerateFPRF(bool single)
B(write_fprf_and_ret); B(write_fprf_and_ret);
} }
void JitArm64::GenerateQuantizedLoadStores() void JitArm64::GenerateQuantizedLoads()
{ {
// X0 is the scale // X0 is the address
// X1 is address // X1 is the scale
// X2 is a temporary on stores
// X30 is LR // X30 is LR
// Q0 is the return for loads // Q0 is the return
// is the register for stores
// Q1 is a temporary // Q1 is a temporary
ARM64Reg addr_reg = ARM64Reg::X1; ARM64Reg addr_reg = ARM64Reg::X0;
ARM64Reg scale_reg = ARM64Reg::X0; ARM64Reg scale_reg = ARM64Reg::X1;
ARM64FloatEmitter float_emit(this); ARM64FloatEmitter float_emit(this);
const u8* start = GetCodePtr(); const u8* start = GetCodePtr();
@ -652,9 +651,21 @@ void JitArm64::GenerateQuantizedLoadStores()
single_load_quantized[5] = loadPairedU16One; single_load_quantized[5] = loadPairedU16One;
single_load_quantized[6] = loadPairedS8One; single_load_quantized[6] = loadPairedS8One;
single_load_quantized[7] = loadPairedS16One; single_load_quantized[7] = loadPairedS16One;
}
// Stores void JitArm64::GenerateQuantizedStores()
start = GetCodePtr(); {
// X0 is the scale
// X1 is the address
// X2 is a temporary
// X30 is LR
// Q0 is the register
// Q1 is a temporary
ARM64Reg scale_reg = ARM64Reg::X0;
ARM64Reg addr_reg = ARM64Reg::X1;
ARM64FloatEmitter float_emit(this);
const u8* start = GetCodePtr();
const u8* storePairedIllegal = GetCodePtr(); const u8* storePairedIllegal = GetCodePtr();
BRK(0x101); BRK(0x101);
const u8* storePairedFloat; const u8* storePairedFloat;