Merge pull request #1794 from FioraAeterna/forceinline
Memory: forceinline read/write hardware functions
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commit
6b88704fd6
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@ -92,7 +92,7 @@ static u32 EFB_Read(const u32 addr)
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static void GenerateDSIException(u32 _EffectiveAddress, bool _bWrite);
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template <typename T, typename U>
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inline void ReadFromHardware(U &_var, const u32 em_address, Memory::XCheckTLBFlag flag)
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__forceinline void ReadFromHardware(U &_var, const u32 em_address, Memory::XCheckTLBFlag flag)
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{
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// TODO: Figure out the fastest order of tests for both read and write (they are probably different).
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if ((em_address & 0xC8000000) == 0xC8000000)
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@ -199,7 +199,7 @@ inline void ReadFromHardware(U &_var, const u32 em_address, Memory::XCheckTLBFla
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template <typename T>
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inline void WriteToHardware(u32 em_address, const T data, Memory::XCheckTLBFlag flag)
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__forceinline void WriteToHardware(u32 em_address, const T data, Memory::XCheckTLBFlag flag)
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{
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// First, let's check for FIFO writes, since they are probably the most common
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// reason we end up in this function:
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@ -742,7 +742,7 @@ void SDRUpdated()
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}
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static u32 LookupTLBPageAddress(const XCheckTLBFlag _Flag, const u32 vpa, u32 *paddr)
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static __forceinline u32 LookupTLBPageAddress(const XCheckTLBFlag _Flag, const u32 vpa, u32 *paddr)
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{
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PowerPC::tlb_entry *tlbe = PowerPC::ppcState.tlb[_Flag == FLAG_OPCODE][(vpa >> HW_PAGE_INDEX_SHIFT) & HW_PAGE_INDEX_MASK];
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if (tlbe[0].tag == (vpa & ~0xfff) && !(tlbe[0].flags & TLB_FLAG_INVALID))
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@ -798,7 +798,7 @@ static u32 LookupTLBPageAddress(const XCheckTLBFlag _Flag, const u32 vpa, u32 *p
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return 0;
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}
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static void UpdateTLBEntry(const XCheckTLBFlag _Flag, UPTE2 PTE2, const u32 vpa)
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static __forceinline void UpdateTLBEntry(const XCheckTLBFlag _Flag, UPTE2 PTE2, const u32 vpa)
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{
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if (_Flag == FLAG_NO_EXCEPTION)
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return;
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@ -833,7 +833,7 @@ void InvalidateTLBEntry(u32 vpa)
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}
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// Page Address Translation
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static u32 TranslatePageAddress(const u32 _Address, const XCheckTLBFlag _Flag)
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static __forceinline u32 TranslatePageAddress(const u32 _Address, const XCheckTLBFlag _Flag)
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{
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// TLB cache
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u32 translatedAddress = 0;
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