From 3fb886141d067a6bc6209d6c8937b8c297cbbbf1 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sat, 15 Apr 2017 07:26:27 +0100 Subject: [PATCH 1/2] JitArm64_LoadStore: Fix bug in writing byte to gather pipe Introduced by c45028a7081f872e87c9d9b42f70f3086aa912f7. --- Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp index 71a7048228..9430e450a9 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp @@ -256,7 +256,7 @@ void JitArm64::SafeStoreFromReg(s32 dest, u32 value, s32 regOffset, u32 flags, s } else { - STRB(INDEX_POST, WA, X0, 1); + STRB(INDEX_POST, RS, X0, 1); } STR(INDEX_UNSIGNED, X0, X1, 0); js.fifoBytesSinceCheck += accessSize >> 3; From 03d07c36ae3e5e13178b896133cdfca9c20a0a41 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sat, 15 Apr 2017 08:20:14 +0100 Subject: [PATCH 2/2] JitArm64: Reserve W30 in SafeStoreFromReg and stfXX Bug introduced in c45028a7081f872e87c9d9b42f70f3086aa912f7. EmitBackpatchRoutine assumes that X30 is available as a temporary. --- Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp | 4 ++-- .../Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp index 9430e450a9..c1e08bdf29 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp @@ -141,7 +141,7 @@ void JitArm64::SafeLoadToReg(u32 dest, s32 addr, s32 offsetReg, u32 flags, s32 o void JitArm64::SafeStoreFromReg(s32 dest, u32 value, s32 regOffset, u32 flags, s32 offset) { // We want to make sure to not get LR as a temp register - gpr.Lock(W0, W1); + gpr.Lock(W0, W1, W30); ARM64Reg RS = gpr.R(value); @@ -282,7 +282,7 @@ void JitArm64::SafeStoreFromReg(s32 dest, u32 value, s32 regOffset, u32 flags, s EmitBackpatchRoutine(flags, jo.fastmem, jo.fastmem, RS, XA, regs_in_use, fprs_in_use); } - gpr.Unlock(W0, W1); + gpr.Unlock(W0, W1, W30); } void JitArm64::lXX(UGeckoInstruction inst) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp index c616b8dfd0..e90f5f6f9c 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp @@ -241,7 +241,7 @@ void JitArm64::stfXX(UGeckoInstruction inst) u32 imm_addr = 0; bool is_immediate = false; - gpr.Lock(W0, W1); + gpr.Lock(W0, W1, W30); fpr.Lock(Q0); bool single = (flags & BackPatchInfo::FLAG_SIZE_F32) && fpr.IsSingle(inst.FS, true); @@ -398,6 +398,6 @@ void JitArm64::stfXX(UGeckoInstruction inst) { EmitBackpatchRoutine(flags, jo.fastmem, jo.fastmem, V0, XA, regs_in_use, fprs_in_use); } - gpr.Unlock(W0, W1); + gpr.Unlock(W0, W1, W30); fpr.Unlock(Q0); }