From d94b00ec3606b63547f1b4f4cb8ab718f82de74a Mon Sep 17 00:00:00 2001 From: JosJuice Date: Sun, 7 Jan 2024 22:59:51 +0100 Subject: [PATCH 1/2] JitArm64: Remove unnecessary locking of W0 in psq_stXX It seems like I made a mistake in 166bd87f70. Locking W0 when jo.memcheck is true is only necessary for load instructions, not store instructions. --- .../Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp index 52bb74658c..4a2c2d3aae 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp @@ -204,7 +204,7 @@ void JitArm64::psq_stXX(UGeckoInstruction inst) } gpr.Lock(ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W30); - if (!js.assumeNoPairedQuantize || jo.memcheck || !jo.fastmem) + if (!js.assumeNoPairedQuantize || !jo.fastmem) gpr.Lock(ARM64Reg::W0); if (!js.assumeNoPairedQuantize && !jo.fastmem) gpr.Lock(ARM64Reg::W3); @@ -283,7 +283,7 @@ void JitArm64::psq_stXX(UGeckoInstruction inst) gpr.Unlock(ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W30); fpr.Unlock(ARM64Reg::Q0); - if (!js.assumeNoPairedQuantize || jo.memcheck || !jo.fastmem) + if (!js.assumeNoPairedQuantize || !jo.fastmem) gpr.Unlock(ARM64Reg::W0); if (!js.assumeNoPairedQuantize && !jo.fastmem) gpr.Unlock(ARM64Reg::W3); From f2145c91e78ff2ae68e390deba504469ba06540b Mon Sep 17 00:00:00 2001 From: JosJuice Date: Sun, 7 Jan 2024 23:01:38 +0100 Subject: [PATCH 2/2] JitArm64: Update register comments in psq_lXX/psq_stXX This was also overlooked in 166bd87f70. --- .../PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp index 4a2c2d3aae..5d1e561eef 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp @@ -27,9 +27,9 @@ void JitArm64::psq_lXX(UGeckoInstruction inst) !(m_ppc_state.feature_flags & FEATURE_FLAG_MSR_DR)); // X30 is LR - // X0 is the address - // X1 contains the scale - // X2 is a temporary + // X0 is a temporary + // X1 is the address + // X2 is the scale // Q0 is the return register // Q1 is a temporary const s32 offset = inst.SIMM_12; @@ -156,8 +156,9 @@ void JitArm64::psq_stXX(UGeckoInstruction inst) !(m_ppc_state.feature_flags & FEATURE_FLAG_MSR_DR)); // X30 is LR - // X0 contains the scale - // X1 is the address + // X0 is a temporary + // X1 is the scale + // X2 is the address // Q0 is the store register const s32 offset = inst.SIMM_12;