From 69c14d6ec39815db22c8a246b9fffb5beb5f5931 Mon Sep 17 00:00:00 2001 From: JosJuice Date: Sat, 23 Jan 2021 20:13:45 +0100 Subject: [PATCH] JitArm64: Fix frspx with single precision source I haven't observed this breaking any game, but it didn't match the behavior of the interpreter as far as I could tell from reading the code, in that denormals weren't being flushed. --- .../Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp index 7ba7dd12ea..4410ecd564 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp @@ -258,7 +258,7 @@ void JitArm64::frspx(UGeckoInstruction inst) const u32 d = inst.FD; const bool single = fpr.IsSingle(b, true); - if (single) + if (single && js.fpr_is_store_safe[b]) { // Source is already in single precision, so no need to do anything but to copy to PSR1. const ARM64Reg VB = fpr.R(b, RegType::LowerPairSingle); @@ -266,6 +266,9 @@ void JitArm64::frspx(UGeckoInstruction inst) if (b != d) m_float_emit.FMOV(EncodeRegToSingle(VD), EncodeRegToSingle(VB)); + + ASSERT_MSG(DYNA_REC, fpr.IsSingle(b, true), + "Register allocation turned singles into doubles in the middle of frspx"); } else { @@ -274,9 +277,6 @@ void JitArm64::frspx(UGeckoInstruction inst) m_float_emit.FCVT(32, 64, EncodeRegToDouble(VD), EncodeRegToDouble(VB)); } - - ASSERT_MSG(DYNA_REC, b == d || single == fpr.IsSingle(b, true), - "Register allocation turned singles into doubles in the middle of frspx"); } void JitArm64::fcmpX(UGeckoInstruction inst)