Document FPSCR fields
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@ -389,32 +389,59 @@ union UReg_FPSCR
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{
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struct
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{
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// Rounding mode (towards: nearest, zero, +inf, -inf)
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u32 RN : 2;
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// Non-IEEE mode enable (aka flush-to-zero)
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u32 NI : 1;
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// Inexact exception enable
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u32 XE : 1;
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// IEEE division by zero exception enable
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u32 ZE : 1;
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// IEEE underflow exception enable
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u32 UE : 1;
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// IEEE overflow exception enable
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u32 OE : 1;
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// Invalid operation exception enable
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u32 VE : 1;
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// Invalid operation exception for integer conversion (sticky)
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u32 VXCVI : 1;
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// Invalid operation exception for square root (sticky)
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u32 VXSQRT : 1;
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// Invalid operation exception for software request (sticky)
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u32 VXSOFT : 1;
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// reserved
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u32 : 1;
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// Floating point result flags (not sticky)
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u32 FPRF : 5;
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// Fraction inexact (not sticky)
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u32 FI : 1;
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// Fraction rounded (not sticky)
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u32 FR : 1;
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// Invalid operation exception for invalid comparison (sticky)
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u32 VXVC : 1;
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// Invalid operation exception for inf * 0 (sticky)
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u32 VXIMZ : 1;
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// Invalid operation exception for 0 / 0 (sticky)
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u32 VXZDZ : 1;
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// Invalid operation exception for int / inf (sticky)
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u32 VXIDI : 1;
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// Invalid operation exception for inf - inf (sticky)
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u32 VXISI : 1;
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// Invalid operation exception for SNaN (sticky)
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u32 VXSNAN : 1;
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// Inexact exception (sticky)
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u32 XX : 1;
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// Division by zero exception (sticky)
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u32 ZX : 1;
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// Underflow exception (sticky)
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u32 UX : 1;
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// Overflow exception (sticky)
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u32 OX : 1;
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// Invalid operation exception summary (not sticky)
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u32 VX : 1;
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// Enabled exception summary (not sticky)
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u32 FEX : 1;
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// Exception summary (sticky)
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u32 FX : 1;
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};
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u32 Hex;
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