Make it so I can easily switch from crappy INFO_LOG to my crappy printf debugging. Added a few noticed notes in the code. Added tabs to the information so it cna be easier for me to debug
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3202 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Sonicadvance1
parent
90e345e40b
commit
683a042ebc
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@ -22,7 +22,21 @@
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#include "EXI_Device.h"
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#include "EXI_DeviceEthernet.h"
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//#define SONICDEBUG
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void DEBUGPRINT (const char * format, ...)
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{
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char buffer[256];
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va_list args;
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va_start (args, format);
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vsprintf (buffer,format, args);
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#ifdef SONICDEBUG
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printf("%s", buffer);
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#else
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INFO_LOG(SP1, buffer);
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#endif
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va_end (args);
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}
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inline u8 makemaskb(int start, int end) {
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return (u8)_rotl((2 << (end - start)) - 1, 7 - end);
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}
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@ -110,21 +124,21 @@ void CEXIETHERNET::recordSendComplete()
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if(mBbaMem[0x08] & BBA_INTERRUPT_SENT)
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{
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mBbaMem[0x09] |= BBA_INTERRUPT_SENT;
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INFO_LOG(SP1, "BBA Send interrupt raised\n");
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DEBUGPRINT( "BBA Send interrupt raised\n");
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exit(0);
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//interrupt.raiseEXI("BBA Send");
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}
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mPacketsSent++;
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}
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bool CEXIETHERNET::sendPacket(u8 *etherpckt, size_t size)
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bool CEXIETHERNET::sendPacket(u8 *etherpckt, int size)
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{
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INFO_LOG(SP1, "Packet: 0x");
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DEBUGPRINT( "Packet: 0x");
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for(int a = 0; a < size; ++a)
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{
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INFO_LOG(SP1, "%02X", etherpckt[a]);
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DEBUGPRINT( "%02X", etherpckt[a]);
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}
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INFO_LOG(SP1, " : Size: %d\n", size);
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DEBUGPRINT( " : Size: %d\n", size);
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/*DWORD numBytesWrit;
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OVERLAPPED overlap;
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ZERO_OBJECT(overlap);
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@ -142,17 +156,17 @@ bool CEXIETHERNET::sendPacket(u8 *etherpckt, size_t size)
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void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
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{
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INFO_LOG(SP1, "IMM Write, size 0x%x, data 0x%x mWriteP 0x%x\n", _uSize, _uData, mWriteP);
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DEBUGPRINT( "IMM Write, size 0x%x, data 0x%x mWriteP 0x%x\n", _uSize, _uData, mWriteP);
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if (mExpectVariableLengthImmWrite)
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{
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INFO_LOG(SP1, "Not doing expecting variable length imm write!\n");
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DEBUGPRINT( "Not doing expecting variable length imm write!\n");
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exit(0);
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}
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else if (mWriteP != INVALID_P)
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{
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if (mWriteP + _uSize > BBAMEM_SIZE)
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{
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INFO_LOG(SP1, "Write error: mWriteP + size = 0x%04X + %i\n", mWriteP, _uSize);
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DEBUGPRINT( "[EEE]Write error: mWriteP + size = 0x%04X + %i\n", mWriteP, _uSize);
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exit(0);
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}
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//BBADEGUB("Write to BBA address 0x%0*X, %i byte%s: 0x%0*X\n",mWriteP >= CB_OFFSET ? 4 : 2, mWriteP, size, (size==1?"":"s"), size*2, data);
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@ -160,7 +174,7 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
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switch (mWriteP)
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{
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case 0x09:
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INFO_LOG(SP1, "mWriteP is %x\n", mWriteP);
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DEBUGPRINT( "\t[INFO]mWriteP is %x\n", mWriteP);
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//BBADEGUB("BBA Interrupt reset 0x%02X & ~(0x%02X) => 0x%02X\n", mBbaMem[0x09], MAKE(BYTE, data), mBbaMem[0x09] & ~MAKE(BYTE, data));
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//assert(_uSize == 1);
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// TODO: Should we swap our data?
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@ -170,26 +184,27 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
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case BBA_NCRA:
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{
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u32 SwappedData = Common::swap32(_uData);
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//u32 SwappedData = _uData;
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// TODO: Should we swap our data?
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if (RISE(BBA_NCRA_RESET))
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{
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// Normal
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// Whinecube did nothing else as well
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INFO_LOG(SP1, "BBA Reset\n");
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DEBUGPRINT( "\t[INFO]BBA Reset\n");
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}
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if (RISE(BBA_NCRA_SR) && isActivated())
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{
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INFO_LOG(SP1, "BBA Start Recieve\n");
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DEBUGPRINT( "\t[INFO]BBA Start Recieve\n");
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exit(0);
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// TODO: Need to make our virtual network device start receiving
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//HWGLE(startRecv());
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}
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if (RISE(BBA_NCRA_ST1))
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{
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INFO_LOG(SP1, "BBA Start Transmit\n");
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DEBUGPRINT( "\t[INFO]BBA Start Transmit\n");
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if (!mReadyToSend)
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{
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INFO_LOG(SP1, "Not ready to send!\n");
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DEBUGPRINT( "\t\t[EEE]Not ready to send!\n");
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exit(0);
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//throw hardware_fatal_exception("BBA Transmit without a packet!");
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}
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@ -198,11 +213,11 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
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mReadyToSend = false;
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//exit(0);
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}
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mBbaMem[0x00] = MAKE(u8, _uData);
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mBbaMem[0x00] = MAKE(u8, SwappedData);
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}
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break;
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case BBA_NWAYC:
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INFO_LOG(SP1, "mWriteP is %x\n", mWriteP);
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DEBUGPRINT( "\t[INFO]mWriteP is %x\n", mWriteP);
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exit(0);
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/*if(data & (BBA_NWAYC_ANE | BBA_NWAYC_ANS_RA))
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{
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@ -214,7 +229,7 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
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}*/
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break;
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case 0x18: //RRP - Receive Buffer Read Page Pointer
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INFO_LOG(SP1, "mWriteP is %x\n", mWriteP);
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DEBUGPRINT( "\t[INFO]mWriteP is %x\n", mWriteP);
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exit(0);
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/*MYASSERT(size == 2 || size == 1);
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mRBRPP = (BYTE)data << 8; //I hope this works with both write sizes.
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@ -222,14 +237,15 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
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HWGLE(checkRecvBuffer());*/
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break;
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case 0x16: //RWP
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INFO_LOG(SP1, "mWriteP is %x\n", mWriteP);
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DEBUGPRINT( "\t[INFO]mWriteP is %x\n", mWriteP);
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exit(0);
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/*MYASSERT(size == 2 || size == 1);
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MYASSERT(data == DWORD((WORD)mCbw.p_write() + CB_OFFSET) >> 8);*/
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break;
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default:
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INFO_LOG(SP1, "Default one!Size 0x%x _uData: 0x%08x Swapped 0x%08x to 0x%x\n", _uSize, _uData, Common::swap32(_uData),mWriteP);
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u32 SwappedData = Common::swap32(_uData);
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DEBUGPRINT( "\t[INFO]Default one!Size 0x%x _uData: 0x%08x Swapped 0x%08x to 0x%x\n", _uSize, _uData, Common::swap32(_uData),mWriteP);
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//u32 SwappedData = Common::swap32(_uData);
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u32 SwappedData = _uData;
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memcpy(mBbaMem + mWriteP, &SwappedData, _uSize);
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mWriteP = mWriteP + _uSize;
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}
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@ -246,31 +262,33 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
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else if ((_uSize == 4 && (_uData & 0xC0000000) == 0xC0000000) || (_uSize == 2 && (_uData & 0x4000) == 0x4000))
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{
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// Write to BBA Register
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INFO_LOG(SP1, "Write to BBA register!\n");
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u32 SwappedData = Common::swap32(_uData);
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//u32 SwappedData = _uData;
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DEBUGPRINT( "\t[INFO]Write to BBA register!\n");
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//u32 SwappedData = Common::swap32(_uData);
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u32 SwappedData = _uData;
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if (_uSize == 4)
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mWriteP = (u8)getbitsw(SwappedData, 16, 23);
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else //size == 2
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mWriteP = (u8)getbitsw(SwappedData & ~0x4000, 16, 23); //Whinecube : Dunno about this...
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// With Size of 4 and data of 0xc0006000 unswapped
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// mWriteP will be 0x0060 unswapped and 0x0000 swapped. Which is correct?
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//Write of size 4 data 0xc0006000 causes write pointer to be set to 0x0000 when swapped.
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// When not swapped, the write pointer is set to 0x0060
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if (mWriteP == 0x48)
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{
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mWriteBuffer.clear();
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mExpectVariableLengthImmWrite = true;
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INFO_LOG(SP1, "Prepared for variable length write to address 0x48\n");
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DEBUGPRINT( "\t\t[INFO]Prepared for variable length write to address 0x48\n");
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}
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else
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{
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INFO_LOG(SP1, "BBA Write pointer set to 0x%0*X\n", _uSize, mWriteP);
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DEBUGPRINT( "\t\t[INFO]BBA Write pointer set to 0x%0*X\n", _uSize, mWriteP);
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//exit(0);
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}
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return;
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}
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else if ((_uSize == 4 && (_uData & 0xC0000000) == 0x80000000) || (_uSize == 2 && (_uData & 0x4000) == 0x0000))
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{
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INFO_LOG(SP1, "Read from BBA register!\n");
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DEBUGPRINT( "\t[INFO]Read from BBA register!\n");
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// If swapped, we get a read from invalid BBA Address 0x2000 in Mario Kart: DD
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// If not swapped, we always end up with an unexpected IMMwrite of 1 byte
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//u32 SwappedData = Common::swap32(_uData);
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u32 SwappedData = _uData;
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// Read from BBA Register!
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@ -279,7 +297,7 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
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mReadP = (u32)getbitsw(SwappedData, 8, 23);
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if (mReadP >= BBAMEM_SIZE)
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{
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INFO_LOG(SP1, "Illegal BBA address: 0x%04X\n", mReadP);
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DEBUGPRINT( "\t\t[EEE]Illegal BBA address: 0x%04X\n", mReadP);
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//if(g::bouehr)
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exit(0);
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//return EXI_UNHANDLED;
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@ -289,26 +307,28 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
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{ //size == 2
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mReadP = (u8)getbitsw(SwappedData, 16, 23);
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}
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// With the data not swapped,after a few reads, nReadP is always 0 in Mario Kart: DD; Size always 2
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// Before that, it does request the MAC address if it's unswapped
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switch (mReadP)
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{
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case 0x20: //MAC address
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INFO_LOG(SP1, "Mac Address!\n");
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DEBUGPRINT( "\t\t[INFO]Mac Address!\n");
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memcpy(mBbaMem + mReadP, mac_address, 6);
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break;
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case 0x01: //Revision ID
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break;
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case 0x16: //RWP - Receive Buffer Write Page Pointer
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INFO_LOG(SP1, "RWP!\n");
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DEBUGPRINT( "\t\t[INFO]RWP!\n");
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exit(0);
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//MAKE(WORD, mBbaMem[mReadP]) = ((WORD)mCbw.p_write() + CB_OFFSET) >> 8;
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break;
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case 0x18: //RRP - Receive Buffer Read Page Pointer
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INFO_LOG(SP1, "RRP!\n");
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DEBUGPRINT( "\t\t[INFO]RRP!\n");
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exit(0);
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//MAKE(WORD, mBbaMem[mReadP]) = (mRBRPP) >> 8;
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break;
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case 0x3A: //bit 1 set if no data available
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INFO_LOG(SP1, "Bit 1 set!\n");
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DEBUGPRINT( "\t\t[INFO]Bit 1 set!\n");
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exit(0);
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//mBbaMem[mReadP] = !mRBEmpty;
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break;
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@ -317,29 +337,29 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
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//mBbaMem[mReadP] = 0x00;
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//if(!sendInProgress())
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mBbaMem[mReadP] &= ~(0x06);
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INFO_LOG(SP1, "mBbaMem[0x%x] &= ~(0x06);! Now %x\n", mReadP, mBbaMem[mReadP]);
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DEBUGPRINT( "\t\t[INFO]mBbaMem[0x%x] &= ~(0x06);! Now 0x%x\n", mReadP, mBbaMem[mReadP]);
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//exit(0);
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break;
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case 0x03:
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mBbaMem[mReadP] = 0x80;
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INFO_LOG(SP1, "mBbaMem[0x%x] = 0x80;! Now %x\n", mReadP, mBbaMem[mReadP]);
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DEBUGPRINT( "\t\t[INFO]mBbaMem[0x%x] = 0x80;! Now %x\n", mReadP, mBbaMem[mReadP]);
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exit(0);
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break;
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}
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//BBADEGUB("BBA Read pointer set to 0x%0*X\n", size, mReadP);
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printf("\t\t[INFO]BBA Read pointer set to 0x%0*X\n", _uSize, mReadP);
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return;
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}
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INFO_LOG(SP1, "Not expecting ImmWrite of size %d\n", _uSize);
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DEBUGPRINT( "\t[EEE]Not expecting ImmWrite of size %d\n", _uSize);
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exit(0);
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}
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u32 CEXIETHERNET::ImmRead(u32 _uSize)
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{
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INFO_LOG(SP1, "IMM Read, size 0x%x\n", _uSize);
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DEBUGPRINT( "IMM Read, size 0x%x\n", _uSize);
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if (mExpectSpecialImmRead)
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{
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// 100% that this returns correctly
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INFO_LOG(SP1, "special IMMRead\n");
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DEBUGPRINT( "\t[INFO]special IMMRead\n");
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mExpectSpecialImmRead = false;
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return mSpecialImmData;
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}
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@ -347,34 +367,34 @@ u32 CEXIETHERNET::ImmRead(u32 _uSize)
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{
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if (mReadP + _uSize > BBAMEM_SIZE)
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{
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INFO_LOG(SP1, "Read error: mReadP + size = 0x%04X + %i\n", mReadP, _uSize);
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DEBUGPRINT( "\t[EEE]Read error: mReadP + size = 0x%04X + %i\n", mReadP, _uSize);
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exit(0);
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}
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u32 uResult = 0;
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memcpy(&uResult, mBbaMem + mReadP, _uSize);
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// TODO: We do as well?
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//uResult = Common::swap32(uResult); //Whinecube : we have a byteswap problem...
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INFO_LOG(SP1, "Read from BBA address 0x%0*X, %i byte%s: 0x%0*X\n",mReadP >= CB_OFFSET ? 4 : 2, mReadP, _uSize, (_uSize==1?"":"s"),_uSize*2, getbitsw(uResult, 0, _uSize * 8 - 1));
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uResult = Common::swap32(uResult); //Whinecube : we have a byteswap problem...
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DEBUGPRINT( "\t[INFO]Read from BBA address 0x%0*X, %i byte%s: 0x%0*X\n",mReadP >= CB_OFFSET ? 4 : 2, mReadP, _uSize, (_uSize==1?"":"s"),_uSize*2, getbitsw(uResult, 0, _uSize * 8 - 1));
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mReadP = mReadP + _uSize;
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return uResult;
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}
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else
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{
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INFO_LOG(SP1, "Unhandled IMM read of %d bytes\n", _uSize);
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DEBUGPRINT( "\t[EEE]Unhandled IMM read of %d bytes\n", _uSize);
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}
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INFO_LOG(SP1, "Not Expecting IMMRead of size %d!\n", _uSize);
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DEBUGPRINT( "[EEE]Not Expecting IMMRead of size %d!\n", _uSize);
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exit(0);
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}
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void CEXIETHERNET::DMAWrite(u32 _uAddr, u32 _uSize)
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{
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INFO_LOG(SP1, "DMAW\n");
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DEBUGPRINT( "DMAW\n");
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exit(0);
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}
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void CEXIETHERNET::DMARead(u32 _uAddr, u32 _uSize)
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{
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INFO_LOG(SP1, "DMAR\n");
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DEBUGPRINT( "DMAR\n");
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exit(0);
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};
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@ -87,7 +87,7 @@ private:
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};
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void recordSendComplete();
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bool sendPacket(u8 *etherpckt, size_t size);
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bool sendPacket(u8 *etherpckt, int size);
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};
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enum {
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