Commit r5970 part #4: Merge some loops in PPCAnalyst::Flatten()
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@5976 8ced0084-cf51-0410-be5f-012b33b47a6e
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dok.slade
parent
16129f6f6d
commit
673f18837b
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@ -296,6 +296,13 @@ u32 Flatten(u32 address, int *realsize, BlockStats *st, BlockRegStats *gpa, Bloc
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gpa->any = true;
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gpa->any = true;
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fpa->any = false;
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fpa->any = false;
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for (int i = 0; i < 32; i++)
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{
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gpa->firstRead[i] = -1;
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gpa->firstWrite[i] = -1;
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gpa->numReads[i] = 0;
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gpa->numWrites[i] = 0;
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}
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u32 blockstart = address;
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u32 blockstart = address;
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int maxsize = blockSize;
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int maxsize = blockSize;
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@ -307,7 +314,8 @@ u32 Flatten(u32 address, int *realsize, BlockStats *st, BlockRegStats *gpa, Bloc
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CodeOp *code = buffer->codebuffer;
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CodeOp *code = buffer->codebuffer;
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bool foundExit = false;
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bool foundExit = false;
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// Flatten! (Currently just copies, following branches is disabled)
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// Do analysis of the code, look for dependencies etc
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int numSystemInstructions = 0;
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for (int i = 0; i < maxsize; i++)
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for (int i = 0; i < maxsize; i++)
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{
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{
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num_inst++;
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num_inst++;
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@ -326,6 +334,106 @@ u32 Flatten(u32 address, int *realsize, BlockStats *st, BlockRegStats *gpa, Bloc
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if (opinfo)
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if (opinfo)
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numCycles += opinfo->numCyclesMinusOne + 1;
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numCycles += opinfo->numCyclesMinusOne + 1;
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_assert_msg_(POWERPC, opinfo != 0, "Invalid Op - Error flattening %08x op %08x", address + i*4, inst.hex);
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_assert_msg_(POWERPC, opinfo != 0, "Invalid Op - Error flattening %08x op %08x", address + i*4, inst.hex);
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code[i].wantsCR0 = false;
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code[i].wantsCR1 = false;
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code[i].wantsPS1 = false;
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int flags = opinfo->flags;
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if (flags & FL_USE_FPU)
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fpa->any = true;
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if (flags & FL_TIMER)
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gpa->anyTimer = true;
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// Does the instruction output CR0?
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if (flags & FL_RC_BIT)
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code[i].outputCR0 = inst.hex & 1; //todo fix
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else if ((flags & FL_SET_CRn) && inst.CRFD == 0)
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code[i].outputCR0 = true;
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else
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code[i].outputCR0 = (flags & FL_SET_CR0) ? true : false;
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// Does the instruction output CR1?
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if (flags & FL_RC_BIT_F)
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code[i].outputCR1 = inst.hex & 1; //todo fix
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else if ((flags & FL_SET_CRn) && inst.CRFD == 1)
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code[i].outputCR1 = true;
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else
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code[i].outputCR1 = (flags & FL_SET_CR1) ? true : false;
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int numOut = 0;
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int numIn = 0;
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if (flags & FL_OUT_A)
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{
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code[i].regsOut[numOut++] = inst.RA;
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gpa->SetOutputRegister(inst.RA, i);
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}
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if (flags & FL_OUT_D)
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{
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code[i].regsOut[numOut++] = inst.RD;
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gpa->SetOutputRegister(inst.RD, i);
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}
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if (flags & FL_OUT_S)
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{
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code[i].regsOut[numOut++] = inst.RS;
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gpa->SetOutputRegister(inst.RS, i);
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}
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if ((flags & FL_IN_A) || ((flags & FL_IN_A0) && inst.RA != 0))
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{
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code[i].regsIn[numIn++] = inst.RA;
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gpa->SetInputRegister(inst.RA, i);
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}
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if (flags & FL_IN_B)
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{
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code[i].regsIn[numIn++] = inst.RB;
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gpa->SetInputRegister(inst.RB, i);
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}
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if (flags & FL_IN_C)
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{
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code[i].regsIn[numIn++] = inst.RC;
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gpa->SetInputRegister(inst.RC, i);
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}
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if (flags & FL_IN_S)
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{
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code[i].regsIn[numIn++] = inst.RS;
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gpa->SetInputRegister(inst.RS, i);
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}
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// Set remaining register slots as unused (-1)
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for (int j = numIn; j < 3; j++)
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code[i].regsIn[j] = -1;
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for (int j = numOut; j < 2; j++)
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code[i].regsOut[j] = -1;
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for (int j = 0; j < 3; j++)
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code[i].fregsIn[j] = -1;
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code[i].fregOut = -1;
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switch (opinfo->type)
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{
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case OPTYPE_INTEGER:
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case OPTYPE_LOAD:
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case OPTYPE_STORE:
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break;
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case OPTYPE_FPU:
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break;
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case OPTYPE_LOADFP:
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break;
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case OPTYPE_BRANCH:
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if (code[i].inst.hex == 0x4e800020)
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{
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// For analysis purposes, we can assume that blr eats flags.
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code[i].outputCR0 = true;
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code[i].outputCR1 = true;
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}
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break;
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case OPTYPE_SYSTEM:
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case OPTYPE_SYSTEMFP:
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numSystemInstructions++;
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break;
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}
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bool follow = false;
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bool follow = false;
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u32 destination;
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u32 destination;
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if (inst.OPCD == 18 && blockSize > 1)
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if (inst.OPCD == 18 && blockSize > 1)
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@ -362,146 +470,6 @@ u32 Flatten(u32 address, int *realsize, BlockStats *st, BlockRegStats *gpa, Bloc
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NOTICE_LOG(POWERPC, "Analyzer ERROR - Function %08x too big, size is 0x%08x", blockstart, address-blockstart);
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NOTICE_LOG(POWERPC, "Analyzer ERROR - Function %08x too big, size is 0x%08x", blockstart, address-blockstart);
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st->numCycles = numCycles;
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st->numCycles = numCycles;
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// Do analysis of the code, look for dependencies etc
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int numSystemInstructions = 0;
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for (int i = 0; i < 32; i++)
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{
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gpa->firstRead[i] = -1;
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gpa->firstWrite[i] = -1;
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gpa->numReads[i] = 0;
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gpa->numWrites[i] = 0;
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}
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gpa->any = true;
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for (int i = 0; i < num_inst; i++)
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{
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UGeckoInstruction inst = code[i].inst;
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code[i].wantsCR0 = false;
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code[i].wantsCR1 = false;
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code[i].wantsPS1 = false;
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const GekkoOPInfo *opinfo = code[i].opinfo;
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_assert_msg_(POWERPC, opinfo != 0, "Invalid Op - Error scanning %08x op %08x",address+i*4,inst.hex);
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int flags = opinfo->flags;
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if (flags & FL_USE_FPU)
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fpa->any = true;
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if (flags & FL_TIMER)
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gpa->anyTimer = true;
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// Does the instruction output CR0?
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if (flags & FL_RC_BIT)
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code[i].outputCR0 = inst.hex & 1; //todo fix
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else if ((flags & FL_SET_CRn) && inst.CRFD == 0)
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code[i].outputCR0 = true;
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else
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code[i].outputCR0 = (flags & FL_SET_CR0) ? true : false;
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// Does the instruction output CR1?
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if (flags & FL_RC_BIT_F)
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code[i].outputCR1 = inst.hex & 1; //todo fix
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else if ((flags & FL_SET_CRn) && inst.CRFD == 1)
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code[i].outputCR1 = true;
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else
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code[i].outputCR1 = (flags & FL_SET_CR1) ? true : false;
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for (int j = 0; j < 3; j++)
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{
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code[i].fregsIn[j] = -1;
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code[i].regsIn[j] = -1;
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}
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for (int j = 0; j < 2; j++)
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code[i].regsOut[j] = -1;
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code[i].fregOut = -1;
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int numOut = 0;
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int numIn = 0;
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if (flags & FL_OUT_A)
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{
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code[i].regsOut[numOut++] = inst.RA;
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gpa->numWrites[inst.RA]++;
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}
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if (flags & FL_OUT_D)
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{
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code[i].regsOut[numOut++] = inst.RD;
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gpa->numWrites[inst.RD]++;
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}
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if (flags & FL_OUT_S)
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{
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code[i].regsOut[numOut++] = inst.RS;
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gpa->numWrites[inst.RS]++;
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}
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if ((flags & FL_IN_A) || ((flags & FL_IN_A0) && inst.RA != 0))
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{
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code[i].regsIn[numIn++] = inst.RA;
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gpa->numReads[inst.RA]++;
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}
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if (flags & FL_IN_B)
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{
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code[i].regsIn[numIn++] = inst.RB;
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gpa->numReads[inst.RB]++;
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}
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if (flags & FL_IN_C)
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{
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code[i].regsIn[numIn++] = inst.RC;
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gpa->numReads[inst.RC]++;
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}
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if (flags & FL_IN_S)
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{
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code[i].regsIn[numIn++] = inst.RS;
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gpa->numReads[inst.RS]++;
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}
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switch (opinfo->type)
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{
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case OPTYPE_INTEGER:
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case OPTYPE_LOAD:
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case OPTYPE_STORE:
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break;
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case OPTYPE_FPU:
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break;
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case OPTYPE_LOADFP:
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break;
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case OPTYPE_BRANCH:
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if (code[i].inst.hex == 0x4e800020)
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{
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// For analysis purposes, we can assume that blr eats flags.
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code[i].outputCR0 = true;
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code[i].outputCR1 = true;
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}
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break;
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case OPTYPE_SYSTEM:
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case OPTYPE_SYSTEMFP:
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numSystemInstructions++;
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break;
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}
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for (int j = 0; j < numIn; j++)
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{
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int r = code[i].regsIn[j];
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if (r < 0 || r > 31)
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PanicAlert("wtf");
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if (gpa->firstRead[r] == -1)
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gpa->firstRead[r] = (short)(i);
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gpa->lastRead[r] = (short)(i);
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gpa->numReads[r]++;
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}
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for (int j = 0; j < numOut; j++)
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{
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int r = code[i].regsOut[j];
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if (r < 0 || r > 31)
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PanicAlert("wtf");
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if (gpa->firstWrite[r] == -1)
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gpa->firstWrite[r] = (short)(i);
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gpa->lastWrite[r] = (short)(i);
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gpa->numWrites[r]++;
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}
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}
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// Instruction Reordering Pass
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// Instruction Reordering Pass
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if (blockSize > 1)
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if (blockSize > 1)
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{
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{
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@ -530,7 +498,7 @@ u32 Flatten(u32 address, int *realsize, BlockStats *st, BlockRegStats *gpa, Bloc
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bool wantsCR0 = true;
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bool wantsCR0 = true;
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bool wantsCR1 = true;
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bool wantsCR1 = true;
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bool wantsPS1 = true;
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bool wantsPS1 = true;
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for (int i = num_inst; i; i--)
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for (int i = num_inst - 1; i >= 0; i--)
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{
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{
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if (code[i].outputCR0)
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if (code[i].outputCR0)
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wantsCR0 = false;
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wantsCR0 = false;
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@ -77,6 +77,20 @@ struct BlockRegStats
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int GetUseRange(int reg) {
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int GetUseRange(int reg) {
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return max(lastRead[reg], lastWrite[reg]) -
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return max(lastRead[reg], lastWrite[reg]) -
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min(firstRead[reg], firstWrite[reg]);}
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min(firstRead[reg], firstWrite[reg]);}
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inline void SetInputRegister(int reg, short opindex) {
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if (firstRead[reg] == -1)
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firstRead[reg] = (short)(opindex);
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lastRead[reg] = (short)(opindex);
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numReads[reg]++;
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}
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inline void SetOutputRegister(int reg, short opindex) {
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if (firstWrite[reg] == -1)
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firstWrite[reg] = (short)(opindex);
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lastWrite[reg] = (short)(opindex);
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numWrites[reg]++;
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}
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};
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};
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