Does anyone know any game that requires the "Clear FIFO BP on Rising Edge"?
Because commenting out this behavior fixes Silent Hill Shattered Memories. If this commit breaks any game, please report. PS: There is a EnterCriticalSection in fifo.cpp, which performs the Read Access, but there is no EnterCriticalSection in CommandProcessor.cpp which performs the Write Access, so how can we guarantee the Write Access is atomic? git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4694 8ced0084-cf51-0410-be5f-012b33b47a6e
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ayuanx
parent
c46b289b2e
commit
66b1eb1f08
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@ -77,65 +77,16 @@
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#include "ChunkFile.h"
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#include "CommandProcessor.h"
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namespace CommandProcessor
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{
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int et_UpdateInterrupts;
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// look for 1002 verts, breakpoint there, see why next draw is flushed
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// TODO(ector): Warn on bbox read/write
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// Fifo Status Register
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union UCPStatusReg
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{
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struct
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{
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unsigned OverflowHiWatermark : 1;
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unsigned UnderflowLoWatermark : 1;
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unsigned ReadIdle : 1;
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unsigned CommandIdle : 1;
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unsigned Breakpoint : 1;
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unsigned : 11;
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};
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u16 Hex;
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UCPStatusReg() {Hex = 0; }
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UCPStatusReg(u16 _hex) {Hex = _hex; }
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};
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// Fifo Control Register
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union UCPCtrlReg
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{
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struct
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{
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unsigned GPReadEnable : 1;
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unsigned CPIntEnable : 1;
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unsigned FifoOverflowIntEnable : 1;
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unsigned FifoUnderflowIntEnable : 1;
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unsigned GPLinkEnable : 1;
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unsigned BPEnable : 1;
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unsigned : 10;
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};
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u16 Hex;
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UCPCtrlReg() {Hex = 0; }
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UCPCtrlReg(u16 _hex) {Hex = _hex; }
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};
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// Fifo Control Register
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union UCPClearReg
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{
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struct
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{
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unsigned ClearFifoOverflow : 1;
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unsigned ClearFifoUnderflow : 1;
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unsigned ClearMetrices : 1;
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unsigned : 13;
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};
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u16 Hex;
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UCPClearReg() {Hex = 0; }
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UCPClearReg(u16 _hex) {Hex = _hex; }
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};
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// STATE_TO_SAVE
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// variables
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SCPFifoStruct fifo;
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UCPStatusReg m_CPStatusReg;
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UCPCtrlReg m_CPCtrlReg;
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UCPClearReg m_CPClearReg;
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@ -146,16 +97,9 @@ int m_bboxright;
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int m_bboxbottom;
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u16 m_tokenReg;
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SCPFifoStruct fifo; //This one is shared between gfx thread and emulator thread
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static u32 fake_GPWatchdogLastToken = 0;
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static Common::Event s_fifoIdleEvent;
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enum
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{
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GATHER_PIPE_SIZE = 32,
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INT_CAUSE_CP = 0x800
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};
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void DoState(PointerWrap &p)
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{
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p.Do(m_CPStatusReg);
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@ -169,10 +113,6 @@ void DoState(PointerWrap &p)
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p.Do(fifo);
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}
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// function
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void UpdateFifoRegister();
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void UpdateInterrupts();
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//inline void WriteLow (u32& _reg, u16 lowbits) {_reg = (_reg & 0xFFFF0000) | lowbits;}
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//inline void WriteHigh(u32& _reg, u16 highbits) {_reg = (_reg & 0x0000FFFF) | ((u32)highbits << 16);}
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inline void WriteLow (volatile u32& _reg, u16 lowbits) {Common::AtomicStore(_reg,(_reg & 0xFFFF0000) | lowbits);}
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@ -181,8 +121,6 @@ inline void WriteHigh(volatile u32& _reg, u16 highbits) {Common::AtomicStore(_re
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inline u16 ReadLow (u32 _reg) {return (u16)(_reg & 0xFFFF);}
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inline u16 ReadHigh (u32 _reg) {return (u16)(_reg >> 16);}
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int et_UpdateInterrupts;
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// for GP watchdog hack
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void IncrementGPWDToken()
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{
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@ -199,6 +137,10 @@ void WaitForFrameFinish()
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fake_GPWatchdogLastToken = fifo.Fake_GPWDToken;
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}
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bool AllowIdleSkipping()
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{
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return !g_VideoInitialize.bOnThread || (!m_CPCtrlReg.CPIntEnable && !m_CPCtrlReg.BPEnable);
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}
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void UpdateInterrupts_Wrapper(u64 userdata, int cyclesLate)
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{
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@ -231,8 +173,6 @@ void Init()
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et_UpdateInterrupts = g_VideoInitialize.pRegisterEvent("UpdateInterrupts", UpdateInterrupts_Wrapper);
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}
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void Shutdown()
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{
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s_fifoIdleEvent.Shutdown();
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@ -342,11 +282,6 @@ void Read16(u16& _rReturnValue, const u32 _Address)
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}
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}
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bool AllowIdleSkipping()
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{
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return !g_VideoInitialize.bOnThread || (!m_CPCtrlReg.CPIntEnable && !m_CPCtrlReg.BPEnable);
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}
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void Write16(const u16 _Value, const u32 _Address)
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{
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INFO_LOG(COMMANDPROCESSOR, "(write16): 0x%04x @ 0x%08x",_Value,_Address);
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@ -423,10 +358,6 @@ void Write16(const u16 _Value, const u32 _Address)
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{
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UCPCtrlReg tmpCtrl(_Value);
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Common::AtomicStore(fifo.bFF_GPReadEnable, tmpCtrl.GPReadEnable);
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Common::AtomicStore(fifo.bFF_GPLinkEnable, tmpCtrl.GPLinkEnable);
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Common::AtomicStore(fifo.bFF_BPEnable, tmpCtrl.BPEnable);
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// TOCHECK (mb2): could BP irq be cleared with w16 to STATUS_REGISTER?
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// funny hack: eg in MP1 if we disable the clear breakpoint ability by commenting this block
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// the game is of course faster but looks stable too.
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@ -437,16 +368,27 @@ void Write16(const u16 _Value, const u32 _Address)
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// BP interrupt is cleared here
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//if (m_CPCtrlReg.CPIntEnable && !tmpCtrl.Hex) // falling edge
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// Why do we need the rising edge? Making it falling egde fixes Silent Hill Shattered Memories
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// It seems the clear on rising edge makes a dead lock between CPU & GPU
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// Don't we need a Thread Synchronization Mechanism here?
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// Otherwise how do we guarantee the fifo access (on a whole entry) is atomic?
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//
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if (m_CPCtrlReg.CPIntEnable && !tmpCtrl.Hex) // falling edge
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// raising edge or falling egde
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if ((!m_CPCtrlReg.CPIntEnable && tmpCtrl.CPIntEnable) || (m_CPCtrlReg.CPIntEnable && !tmpCtrl.Hex))
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//if ((!m_CPCtrlReg.CPIntEnable && tmpCtrl.CPIntEnable) || (m_CPCtrlReg.CPIntEnable && !tmpCtrl.Hex))
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{
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m_CPStatusReg.Breakpoint = 0;
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Common::AtomicStore(fifo.bFF_Breakpoint, 0);
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}
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Common::AtomicStore(fifo.bFF_GPReadEnable, tmpCtrl.GPReadEnable);
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Common::AtomicStore(fifo.bFF_GPLinkEnable, tmpCtrl.GPLinkEnable);
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Common::AtomicStore(fifo.bFF_BPEnable, tmpCtrl.BPEnable);
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m_CPCtrlReg.Hex = tmpCtrl.Hex;
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UpdateInterrupts();
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to CTRL_REGISTER : %04x", _Value);
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DEBUG_LOG(COMMANDPROCESSOR, "\t GPREAD %s | CPULINK %s | BP %s || CPIntEnable %s | OvF %s | UndF %s"
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, fifo.bFF_GPReadEnable ? "ON" : "OFF"
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@ -456,7 +398,6 @@ void Write16(const u16 _Value, const u32 _Address)
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, m_CPCtrlReg.FifoOverflowIntEnable ? "ON" : "OFF"
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, m_CPCtrlReg.FifoUnderflowIntEnable ? "ON" : "OFF"
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);
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}
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break;
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@ -641,7 +582,6 @@ void STACKALIGN GatherPipeBursted()
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}
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}
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// This is mostly used in single core mode
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void CatchUpGPU()
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{
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@ -23,8 +23,12 @@
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class PointerWrap;
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extern bool MT;
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namespace CommandProcessor
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{
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extern SCPFifoStruct fifo; //This one is shared between gfx thread and emulator thread
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// internal hardware addresses
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enum
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{
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@ -63,7 +67,61 @@ enum
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CP_PERF3_H = 0x4e,
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};
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extern SCPFifoStruct fifo;
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enum
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{
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GATHER_PIPE_SIZE = 32,
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INT_CAUSE_CP = 0x800
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};
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// Fifo Status Register
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union UCPStatusReg
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{
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struct
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{
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unsigned OverflowHiWatermark : 1;
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unsigned UnderflowLoWatermark : 1;
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unsigned ReadIdle : 1;
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unsigned CommandIdle : 1;
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unsigned Breakpoint : 1;
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unsigned : 11;
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};
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u16 Hex;
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UCPStatusReg() {Hex = 0; }
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UCPStatusReg(u16 _hex) {Hex = _hex; }
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};
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// Fifo Control Register
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union UCPCtrlReg
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{
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struct
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{
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unsigned GPReadEnable : 1;
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unsigned CPIntEnable : 1;
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unsigned FifoOverflowIntEnable : 1;
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unsigned FifoUnderflowIntEnable : 1;
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unsigned GPLinkEnable : 1;
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unsigned BPEnable : 1;
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unsigned : 10;
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};
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u16 Hex;
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UCPCtrlReg() {Hex = 0; }
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UCPCtrlReg(u16 _hex) {Hex = _hex; }
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};
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// Fifo Control Register
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union UCPClearReg
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{
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struct
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{
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unsigned ClearFifoOverflow : 1;
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unsigned ClearFifoUnderflow : 1;
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unsigned ClearMetrices : 1;
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unsigned : 13;
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};
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u16 Hex;
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UCPClearReg() {Hex = 0; }
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UCPClearReg(u16 _hex) {Hex = _hex; }
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};
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// Init
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void Init();
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@ -79,6 +137,7 @@ void Write32(const u32 _Data, const u32 _Address);
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// for CGPFIFO
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void CatchUpGPU();
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void GatherPipeBursted();
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void UpdateFifoRegister();
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void UpdateInterrupts();
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void UpdateInterruptsFromVideoPlugin();
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void SetFifoIdleFromVideoPlugin();
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