VideoCommon: drop CP MMIO registers that were probably added in the wrong place
I think someone confused these with the actual token and bounding box registers in PE, which were added later. In CP they never did anything and it's suspicious that they have the same addresses as their PE counterparts. On real hardware they always read as zero.
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@ -98,7 +98,7 @@ static size_t s_state_writes_in_queue;
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static std::condition_variable s_state_write_queue_is_empty;
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// Don't forget to increase this after doing changes on the savestate system
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constexpr u32 STATE_VERSION = 169; // Last changed in PR 13074
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constexpr u32 STATE_VERSION = 170; // Last changed in PR 13219
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// Increase this if the StateExtendedHeader definition changes
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constexpr u32 EXTENDED_HEADER_VERSION = 1; // Last changed in PR 12217
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@ -87,11 +87,6 @@ void CommandProcessorManager::DoState(PointerWrap& p)
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p.Do(m_cp_status_reg);
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p.Do(m_cp_ctrl_reg);
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p.Do(m_cp_clear_reg);
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p.Do(m_bbox_left);
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p.Do(m_bbox_top);
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p.Do(m_bbox_right);
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p.Do(m_bbox_bottom);
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p.Do(m_token_reg);
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m_fifo.DoState(p);
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p.Do(m_interrupt_set);
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@ -118,13 +113,6 @@ void CommandProcessorManager::Init()
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m_cp_clear_reg.Hex = 0;
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m_bbox_left = 0;
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m_bbox_top = 0;
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m_bbox_right = 640;
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m_bbox_bottom = 480;
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m_token_reg = 0;
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m_fifo.Init();
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m_is_fifo_error_seen = false;
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@ -138,8 +126,6 @@ void CommandProcessorManager::Init()
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void CommandProcessorManager::RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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{
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constexpr u16 WMASK_NONE = 0x0000;
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constexpr u16 WMASK_ALL = 0xffff;
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constexpr u16 WMASK_LO_ALIGN_32BIT = 0xffe0;
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const u16 WMASK_HI_RESTRICT = GetPhysicalAddressMask(m_system.IsWii()) >> 16;
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@ -153,13 +139,6 @@ void CommandProcessorManager::RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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// For _HI registers in this range, only bits 0x03ff can be set on GCN and 0x1fff on Wii
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u16 wmask;
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} directly_mapped_vars[] = {
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{FIFO_TOKEN_REGISTER, &m_token_reg, false, WMASK_ALL},
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// Bounding box registers are read only.
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{FIFO_BOUNDING_BOX_LEFT, &m_bbox_left, true, WMASK_NONE},
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{FIFO_BOUNDING_BOX_RIGHT, &m_bbox_right, true, WMASK_NONE},
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{FIFO_BOUNDING_BOX_TOP, &m_bbox_top, true, WMASK_NONE},
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{FIFO_BOUNDING_BOX_BOTTOM, &m_bbox_bottom, true, WMASK_NONE},
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{FIFO_BASE_LO, MMIO::Utils::LowPart(&m_fifo.CPBase), false, WMASK_LO_ALIGN_32BIT},
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{FIFO_BASE_HI, MMIO::Utils::HighPart(&m_fifo.CPBase), false, WMASK_HI_RESTRICT},
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{FIFO_END_LO, MMIO::Utils::LowPart(&m_fifo.CPEnd), false, WMASK_LO_ALIGN_32BIT},
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@ -60,11 +60,6 @@ enum
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CTRL_REGISTER = 0x02,
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CLEAR_REGISTER = 0x04,
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PERF_SELECT = 0x06,
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FIFO_TOKEN_REGISTER = 0x0E,
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FIFO_BOUNDING_BOX_LEFT = 0x10,
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FIFO_BOUNDING_BOX_RIGHT = 0x12,
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FIFO_BOUNDING_BOX_TOP = 0x14,
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FIFO_BOUNDING_BOX_BOTTOM = 0x16,
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FIFO_BASE_LO = 0x20,
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FIFO_BASE_HI = 0x22,
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FIFO_END_LO = 0x24,
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