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Jit_Integer: Port subfic to new register cache interface

This commit is contained in:
MerryMage 2018-10-15 21:00:56 +01:00
parent 33812319ac
commit 64c29ab942
1 changed files with 11 additions and 9 deletions
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20
Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
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@ -899,40 +899,42 @@ void Jit64::subfic(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITIntegerOff); JITDISABLE(bJITIntegerOff);
int a = inst.RA, d = inst.RD; int a = inst.RA, d = inst.RD;
gpr.Lock(a, d);
gpr.BindToRegister(d, a == d, true); RCOpArg Ra = gpr.Use(a, RCMode::Read);
RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
RegCache::Realize(Ra, Rd);
int imm = inst.SIMM_16; int imm = inst.SIMM_16;
if (d == a) if (d == a)
{ {
if (imm == 0) if (imm == 0)
{ {
// Flags act exactly like subtracting from 0 // Flags act exactly like subtracting from 0
NEG(32, gpr.R(d)); NEG(32, Rd);
// Output carry is inverted // Output carry is inverted
FinalizeCarry(CC_NC); FinalizeCarry(CC_NC);
} }
else if (imm == -1) else if (imm == -1)
{ {
NOT(32, gpr.R(d)); NOT(32, Rd);
// CA is always set in this case // CA is always set in this case
FinalizeCarry(true); FinalizeCarry(true);
} }
else else
{ {
NOT(32, gpr.R(d)); NOT(32, Rd);
ADD(32, gpr.R(d), Imm32(imm + 1)); ADD(32, Rd, Imm32(imm + 1));
// Output carry is normal // Output carry is normal
FinalizeCarry(CC_C); FinalizeCarry(CC_C);
} }
} }
else else
{ {
MOV(32, gpr.R(d), Imm32(imm)); MOV(32, Rd, Imm32(imm));
SUB(32, gpr.R(d), gpr.R(a)); SUB(32, Rd, Ra);
// Output carry is inverted // Output carry is inverted
FinalizeCarry(CC_NC); FinalizeCarry(CC_NC);
} }
gpr.UnlockAll();
// This instruction has no RC flag // This instruction has no RC flag
} }