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Merge pull request #7467 from MerryMage/lXXx 

Jit_LoadStore: Name indexed condition
This commit is contained in:
Tilka 2018-10-07 20:35:05 +01:00 committed by GitHub
parent 1ab1d41b10 8e3846d844
commit 63dcd33e9c
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 8 additions and 5 deletions
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13
Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp
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@ -159,6 +159,9 @@ void Jit64::lXXx(UGeckoInstruction inst)
else
update = ((inst.OPCD & 1) != 0) && inst.SIMM_16 != 0;
// Determine whether this instruction indexes with inst.RB
const bool indexed = inst.OPCD == 31;
bool storeAddress = false;
s32 loadOffset = 0;
@ -166,7 +169,7 @@ void Jit64::lXXx(UGeckoInstruction inst)
OpArg opAddress;
if (!update && !a)
{
if (inst.OPCD == 31)
if (indexed)
{
if (!gpr.R(b).IsImm())
gpr.BindToRegister(b, true, false);
@ -183,14 +186,14 @@ void Jit64::lXXx(UGeckoInstruction inst)
}
else
{
if ((inst.OPCD != 31) && gpr.R(a).IsImm() && !jo.memcheck)
if (!indexed && gpr.R(a).IsImm() && !jo.memcheck)
{
u32 val = gpr.R(a).Imm32() + inst.SIMM_16;
opAddress = Imm32(val);
if (update)
gpr.SetImmediate32(a, val);
}
else if ((inst.OPCD == 31) && gpr.R(a).IsImm() && gpr.R(b).IsImm() && !jo.memcheck)
else if (indexed && gpr.R(a).IsImm() && gpr.R(b).IsImm() && !jo.memcheck)
{
u32 val = gpr.R(a).Imm32() + gpr.R(b).Imm32();
opAddress = Imm32(val);
@ -200,11 +203,11 @@ void Jit64::lXXx(UGeckoInstruction inst)
else
{
// If we're using reg+reg mode and b is an immediate, pretend we're using constant offset mode
bool use_constant_offset = inst.OPCD != 31 || gpr.R(b).IsImm();
bool use_constant_offset = !indexed || gpr.R(b).IsImm();
s32 offset = 0;
if (use_constant_offset)
offset = inst.OPCD == 31 ? gpr.R(b).SImm32() : (s32)inst.SIMM_16;
offset = indexed ? gpr.R(b).SImm32() : (s32)inst.SIMM_16;
// Depending on whether we have an immediate and/or update, find the optimum way to calculate
// the load address.
if ((update || use_constant_offset) && !jo.memcheck)