[AArch64] Minor performance improvements to paired stores.
We can combine these two ST1 calls in to a single ST1 call. Saves a few cycles in paired stores
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@ -273,8 +273,7 @@ void JitArm64AsmRoutineManager::GenerateCommon()
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float_emit.REV32(8, D0, D0);
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MOVK(addr_reg, ((u64)Memory::base >> 32) & 0xFFFF, SHIFT_32);
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float_emit.ST1(32, Q0, 0, addr_reg, SP);
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float_emit.ST1(32, Q0, 1, addr_reg, SP);
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float_emit.ST1(64, Q0, 0, addr_reg, SP);
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RET(X30);
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SetJumpTarget(argh);
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@ -304,9 +303,9 @@ void JitArm64AsmRoutineManager::GenerateCommon()
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TST(DecodeReg(addr_reg), 6, 1);
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FixupBranch argh = B(CC_NEQ);
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MOVK(addr_reg, ((u64)Memory::base >> 32) & 0xFFFF, SHIFT_32);
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float_emit.ST1(8, Q0, 0, addr_reg, SP);
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float_emit.ST1(8, Q0, 1, addr_reg, SP);
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float_emit.ST1(16, Q0, 0, addr_reg, SP);
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RET(X30);
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SetJumpTarget(argh);
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@ -335,9 +334,9 @@ void JitArm64AsmRoutineManager::GenerateCommon()
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TST(DecodeReg(addr_reg), 6, 1);
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FixupBranch argh = B(CC_NEQ);
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MOVK(addr_reg, ((u64)Memory::base >> 32) & 0xFFFF, SHIFT_32);
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float_emit.ST1(8, Q0, 0, addr_reg, SP);
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float_emit.ST1(8, Q0, 1, addr_reg, SP);
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float_emit.ST1(16, Q0, 0, addr_reg, SP);
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RET(X30);
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SetJumpTarget(argh);
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@ -368,8 +367,7 @@ void JitArm64AsmRoutineManager::GenerateCommon()
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TST(DecodeReg(addr_reg), 6, 1);
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FixupBranch argh = B(CC_NEQ);
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MOVK(addr_reg, ((u64)Memory::base >> 32) & 0xFFFF, SHIFT_32);
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float_emit.ST1(16, Q0, 0, addr_reg, SP);
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float_emit.ST1(16, Q0, 1, addr_reg, SP);
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float_emit.ST1(32, Q0, 0, addr_reg, SP);
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RET(X30);
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SetJumpTarget(argh);
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@ -399,8 +397,7 @@ void JitArm64AsmRoutineManager::GenerateCommon()
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TST(DecodeReg(addr_reg), 6, 1);
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FixupBranch argh = B(CC_NEQ);
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MOVK(addr_reg, ((u64)Memory::base >> 32) & 0xFFFF, SHIFT_32);
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float_emit.ST1(16, Q0, 0, addr_reg, SP);
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float_emit.ST1(16, Q0, 1, addr_reg, SP);
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float_emit.ST1(32, Q0, 0, addr_reg, SP);
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RET(X30);
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SetJumpTarget(argh);
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