diff --git a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp
index c8586d1e22..7b1d6701d9 100644
--- a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp
+++ b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp
@@ -121,7 +121,7 @@ void rti(const UDSPInstruction& opc)
 		ERROR_LOG(DSPLLE, "dsp rti opcode");
 	}
 
-	g_dsp.r[R_SR] = dsp_reg_load_stack(DSP_STACK_D);
+	g_dsp.r[DSP_REG_SR] = dsp_reg_load_stack(DSP_STACK_D);
 	g_dsp.pc = dsp_reg_load_stack(DSP_STACK_C);
 
 	g_dsp.exception_in_progress_hack = false;
@@ -519,7 +519,7 @@ void addarn(const UDSPInstruction& opc)
 	u8 dreg = opc.hex & 0x3;
 	u8 sreg = (opc.hex >> 2) & 0x3;
 
-	g_dsp.r[dreg] += (s16)g_dsp.r[0x04 + sreg];
+	g_dsp.r[dreg] += (s16)g_dsp.r[DSP_REG_IX0 + sreg];
 }
 
 void mulcac(const UDSPInstruction& opc)
@@ -619,11 +619,11 @@ void andc(const UDSPInstruction& opc)
 
 	if ((ac1 & ac2) == 0)
 	{
-		g_dsp.r[R_SR] |= 0x20;  // 0x40?
+		g_dsp.r[DSP_REG_SR] |= 0x20;  // 0x40?
 	}
 	else
 	{
-		g_dsp.r[R_SR] &= ~0x20; // 0x40?
+		g_dsp.r[DSP_REG_SR] &= ~0x20; // 0x40?
 	}
 }
 
@@ -658,11 +658,11 @@ void andfc(const UDSPInstruction& opc)
 
 	if ((val & imm) == imm)
 	{
-		g_dsp.r[R_SR] |= 0x40;
+		g_dsp.r[DSP_REG_SR] |= 0x40;
 	}
 	else
 	{
-		g_dsp.r[R_SR] &= ~0x40;
+		g_dsp.r[DSP_REG_SR] &= ~0x40;
 	}
 }
 
@@ -693,11 +693,11 @@ void andf(const UDSPInstruction& opc)
 
 	if ((val & imm) == 0)
 	{
-		g_dsp.r[R_SR] |= 0x40;
+		g_dsp.r[DSP_REG_SR] |= 0x40;
 	}
 	else
 	{
-		g_dsp.r[R_SR] &= ~0x40;
+		g_dsp.r[DSP_REG_SR] &= ~0x40;
 	}
 }
 
@@ -1158,14 +1158,14 @@ void iar(const UDSPInstruction& opc)
 void sbclr(const UDSPInstruction& opc)
 {
 	u8 bit = (opc.hex & 0xff) + 6;
-	g_dsp.r[R_SR] &= ~(1 << bit);
+	g_dsp.r[DSP_REG_SR] &= ~(1 << bit);
 }
 
 
 void sbset(const UDSPInstruction& opc)
 {
 	u8 bit = (opc.hex & 0xff) + 6;
-	g_dsp.r[R_SR] |= (1 << bit);
+	g_dsp.r[DSP_REG_SR] |= (1 << bit);
 }
 
 
@@ -1199,13 +1199,13 @@ void srbith(const UDSPInstruction& opc)
 	// 40-bit precision? clamping? no idea :(
 	// 40 seems to be the default.
 	case 0xe: // SET40  (really, clear SR's 0x4000?) something about "set 40-bit operation"?
-		g_dsp.r[R_SR] &= ~(1 << 14);
+		g_dsp.r[DSP_REG_SR] &= ~(1 << 14);
 		ERROR_LOG(DSPLLE, "SET40");
 		break;
 
 	case 0xf: // SET16  (really, set SR's 0x4000?) something about "set 16-bit operation"?
 		// that doesnt happen on a real console  << what does this comment mean?
-		g_dsp.r[R_SR] |= (1 << 14);
+		g_dsp.r[DSP_REG_SR] |= (1 << 14);
 		ERROR_LOG(DSPLLE, "SET16");
 		break;
 
diff --git a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.h b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.h
index 0c61db84cb..012bb23275 100644
--- a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.h
+++ b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.h
@@ -21,8 +21,6 @@
 #include "DSPTables.h"
 
 #define DSP_REG_MASK    0x1f
-
-#define R_SR            0x13
 #define FLAG_ENABLE_INTERUPT    11
 
 namespace DSPInterpreter {
diff --git a/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_condition_codes.cpp b/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_condition_codes.cpp
index 1d1884f873..407fee3bc6 100644
--- a/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_condition_codes.cpp
+++ b/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_condition_codes.cpp
@@ -28,49 +28,49 @@ namespace DSPInterpreter {
 
 void Update_SR_Register64(s64 _Value)
 {
-	g_dsp.r[R_SR] &= ~SR_CMP_MASK;
+	g_dsp.r[DSP_REG_SR] &= ~SR_CMP_MASK;
 
 	if (_Value < 0)
 	{
-		g_dsp.r[R_SR] |= 0x8;
+		g_dsp.r[DSP_REG_SR] |= 0x8;
 	}
 
 	if (_Value == 0)
 	{
-		g_dsp.r[R_SR] |= 0x4;
+		g_dsp.r[DSP_REG_SR] |= 0x4;
 	}
 
 	// weird
 	if ((_Value >> 62) == 0)
 	{
-		g_dsp.r[R_SR] |= 0x20;
+		g_dsp.r[DSP_REG_SR] |= 0x20;
 	}
 }
 
 void Update_SR_Register16(s16 _Value)
 {
-	g_dsp.r[R_SR] &= ~SR_CMP_MASK;
+	g_dsp.r[DSP_REG_SR] &= ~SR_CMP_MASK;
 
 	if (_Value < 0)
 	{
-		g_dsp.r[R_SR] |= 0x8;
+		g_dsp.r[DSP_REG_SR] |= 0x8;
 	}
 
 	if (_Value == 0)
 	{
-		g_dsp.r[R_SR] |= 0x4;
+		g_dsp.r[DSP_REG_SR] |= 0x4;
 	}
 
 	// weird
 	if ((_Value >> 14) == 0)
 	{
-		g_dsp.r[R_SR] |= 0x20;
+		g_dsp.r[DSP_REG_SR] |= 0x20;
 	}
 }
 
 int GetMultiplyModifier()
 {
-	if (g_dsp.r[R_SR] & (1 << 13))
+	if (g_dsp.r[DSP_REG_SR] & (1 << 13))
 		return 1;
 	else	
 		return 2;
@@ -88,58 +88,58 @@ bool CheckCondition(u8 _Condition)
 	{
 	case 0x0: //NS - NOT SIGN
 
-		if (!(g_dsp.r[R_SR] & 0x08))
+		if (!(g_dsp.r[DSP_REG_SR] & 0x08))
 			taken = true;
 		break;
 		
 	case 0x1: // S - SIGN
 		
-		if (g_dsp.r[R_SR] & 0x08)
+		if (g_dsp.r[DSP_REG_SR] & 0x08)
 			taken = true;
 		break;
  
 	case 0x2: // G - GREATER
 
-		if ( (!(g_dsp.r[R_SR] & 0x02) || !(g_dsp.r[R_SR] & 0x04)) && !(g_dsp.r[R_SR] & 0x08))
+		if ( (!(g_dsp.r[DSP_REG_SR] & 0x02) || !(g_dsp.r[DSP_REG_SR] & 0x04)) && !(g_dsp.r[DSP_REG_SR] & 0x08))
 			taken = true;
 		break;
 
 	case 0x3: // LE - LESS EQUAL
-		if ((g_dsp.r[R_SR] & 0x02) || (g_dsp.r[R_SR] & 0x04) || (g_dsp.r[R_SR] & 0x08))
+		if ((g_dsp.r[DSP_REG_SR] & 0x02) || (g_dsp.r[DSP_REG_SR] & 0x04) || (g_dsp.r[DSP_REG_SR] & 0x08))
 			taken = true;
 		break;
 
 	case 0x4: // NZ - NOT ZERO
 
-		if (!(g_dsp.r[R_SR] & 0x04))
+		if (!(g_dsp.r[DSP_REG_SR] & 0x04))
 			taken = true;
 		break;
 
 	case 0x5: // Z - ZERO 
 
-		if (g_dsp.r[R_SR] & 0x04)
+		if (g_dsp.r[DSP_REG_SR] & 0x04)
 			taken = true;
 		break;
 
 	case 0x6: // L - LESS
-		if ((g_dsp.r[R_SR] & 0x02) || (g_dsp.r[R_SR] & 0x08))
+		if ((g_dsp.r[DSP_REG_SR] & 0x02) || (g_dsp.r[DSP_REG_SR] & 0x08))
 			taken = true;
 		break;
 
 	case 0x7: // GE - GREATER EQUAL
-		if ( (!(g_dsp.r[R_SR] & 0x02) || (g_dsp.r[R_SR] & 0x04)) && !(g_dsp.r[R_SR] & 0x08))
+		if ( (!(g_dsp.r[DSP_REG_SR] & 0x02) || (g_dsp.r[DSP_REG_SR] & 0x04)) && !(g_dsp.r[DSP_REG_SR] & 0x08))
 		break;
 
 	case 0xc: // LNZ  - LOGIC NOT ZERO
 
-		if (!(g_dsp.r[R_SR] & 0x40))
+		if (!(g_dsp.r[DSP_REG_SR] & 0x40))
 			taken = true;
 
 		break;
 
 	case 0xd: // LZ - LOGIC ZERO
 
-		if (g_dsp.r[R_SR] & 0x40)
+		if (g_dsp.r[DSP_REG_SR] & 0x40)
 			taken = true;
 
 		break;
diff --git a/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_interpreter.cpp b/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_interpreter.cpp
index 8b340c35b4..6ccd1ec611 100644
--- a/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_interpreter.cpp
+++ b/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_interpreter.cpp
@@ -315,7 +315,7 @@ void gdsp_step()
 				_assert_msg_(MASTER_LOG, !g_dsp.exception_in_progress_hack, "assert while exception");
 
 				dsp_reg_store_stack(DSP_STACK_C, g_dsp.pc);
-				dsp_reg_store_stack(DSP_STACK_D, g_dsp.r[R_SR]);
+				dsp_reg_store_stack(DSP_STACK_D, g_dsp.r[DSP_REG_SR]);
 
 				g_dsp.pc = i * 2;
 				g_dsp.exceptions &= ~(1 << i);
diff --git a/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_opcodes_helper.h b/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_opcodes_helper.h
index 2b69a7c63f..91ff31d5b1 100644
--- a/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_opcodes_helper.h
+++ b/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_opcodes_helper.h
@@ -43,12 +43,12 @@
 
 inline void dsp_SR_set_flag(int flag)
 {
-	g_dsp.r[R_SR] |= (1 << flag);
+	g_dsp.r[DSP_REG_SR] |= (1 << flag);
 }
 
 inline bool dsp_SR_is_flag_set(int flag)
 {
-	return (g_dsp.r[R_SR] & (1 << flag)) != 0;
+	return (g_dsp.r[DSP_REG_SR] & (1 << flag)) != 0;
 }
 
 
diff --git a/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_registers.h b/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_registers.h
index 1be367c9c3..eaf99b4c42 100644
--- a/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_registers.h
+++ b/Source/Plugins/Plugin_DSP_LLE-testing/Src/gdsp_registers.h
@@ -27,11 +27,69 @@
 
 #include "Globals.h"
 
-#define DSP_REG_ST0 0x0c
-//#define DSP_REG_ST1 0x0d
-//#define DSP_REG_ST2 0x0e
-//#define DSP_REG_ST3 0x0f
 
+// Register table taken from libasnd
+#define DSP_REG_AR0         0x00    // address registers
+#define DSP_REG_AR1         0x01
+#define DSP_REG_AR2         0x02
+#define DSP_REG_AR3         0x03    // used as jump function selector
+
+#define DSP_REG_IX0         0x04    // LEFT_VOLUME accel
+#define DSP_REG_IX1         0x05    // RIGHT_VOLUME accel
+#define DSP_REG_IX2         0x06    // ADDRH_SMP accel
+#define DSP_REG_IX3         0x07    // ADDRL_SMP accel
+
+#define DSP_REG_R08         0x08    // fixed to 48000 value
+#define DSP_REG_R09         0x09    // problems using this
+#define DSP_REG_R0A         0x0a    // ADDREH_SMP accel
+#define DSP_REG_R0B         0x0b    // ADDREL_SMP accel
+
+#define DSP_REG_ST0         0x0c
+#define DSP_REG_ST1         0x0d
+#define DSP_REG_ST2         0x0e
+#define DSP_REG_ST3         0x0f
+
+#define DSP_REG_CONFIG      0x12
+#define DSP_REG_SR          0x13
+
+#define DSP_REG_PRODL       0x14
+#define DSP_REG_PRODM       0x15
+#define DSP_REG_PRODH       0x16
+#define DSP_REG_PRODM2      0x17 
+
+#define DSP_REG_AXL0        0x18
+#define DSP_REG_AXL1        0x19
+#define DSP_REG_AXH0        0x1A    // SMP_R accel
+#define DSP_REG_AXH1        0x1b    // SMP_L accel
+
+#define DSP_REG_ACC0        0x1c    // accumulator (global)
+#define DSP_REG_ACC1        0x1d
+
+#define DSP_REG_ACL0        0x1c    // Low accumulator
+#define DSP_REG_ACL1        0x1d
+#define DSP_REG_ACM0        0x1e    // Mid accumulator
+#define DSP_REG_ACM1        0x1f
+#define DSP_REG_ACH0        0x10    // Sign extended 8 bit register 0
+#define DSP_REG_ACH1        0x11    // Sign extended 8 bit register 1
+
+// Hardware registers address
+
+#define DSP_REG_DSCR        0xffc9  // DSP DMA Control Reg
+#define DSP_REG_DSBL        0xffcb  // DSP DMA Block Length
+#define DSP_REG_DSPA        0xffcd  // DSP DMA DMEM Address
+#define DSP_REG_DSMAH       0xffce  // DSP DMA Mem Address H
+#define DSP_REG_DSMAL       0xffcf  // DSP DMA Mem Address L
+
+#define DSP_REG_DIRQ        0xfffb  // DSP Irq Rest
+#define DSP_REG_DMBH        0xfffc  // DSP Mailbox H
+#define DSP_REG_DMBL        0xfffd  // DSP Mailbox L
+#define DSP_REG_CMBH        0xfffe  // CPU Mailbox H
+#define DSP_REG_CMBL        0xffff  // CPU Mailbox L
+
+#define DMA_TO_DSP          0
+#define DMA_TO_CPU          1
+
+// Stacks
 #define DSP_STACK_C 0
 #define DSP_STACK_D 1