JitArm64: Add ScopedARM64Reg
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@ -177,6 +177,59 @@ public:
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// Requires unlocking after done
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Arm64Gen::ARM64Reg GetReg();
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class ScopedARM64Reg
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{
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public:
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inline ScopedARM64Reg() = default;
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ScopedARM64Reg(const ScopedARM64Reg&) = delete;
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explicit inline ScopedARM64Reg(Arm64RegCache& cache) : m_reg(cache.GetReg()), m_gpr(&cache) {}
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inline ScopedARM64Reg(Arm64Gen::ARM64Reg reg) : m_reg(reg) {}
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inline ScopedARM64Reg(ScopedARM64Reg&& scoped_reg) { *this = std::move(scoped_reg); }
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inline ~ScopedARM64Reg() { Unlock(); }
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inline ScopedARM64Reg& operator=(const ScopedARM64Reg&) = delete;
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inline ScopedARM64Reg& operator=(Arm64Gen::ARM64Reg reg)
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{
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Unlock();
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m_reg = reg;
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return *this;
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}
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inline ScopedARM64Reg& operator=(ScopedARM64Reg&& scoped_reg)
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{
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// Taking ownership of an existing scoped register, no need to release.
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m_reg = scoped_reg.m_reg;
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m_gpr = scoped_reg.m_gpr;
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scoped_reg.Invalidate();
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return *this;
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}
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inline Arm64Gen::ARM64Reg GetReg() const { return m_reg; }
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inline operator Arm64Gen::ARM64Reg() const { return GetReg(); }
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inline void Unlock()
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{
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// Only unlock the register if GPR is set.
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if (m_gpr != nullptr)
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{
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m_gpr->Unlock(m_reg);
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}
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Invalidate();
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}
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private:
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inline void Invalidate()
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{
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m_reg = Arm64Gen::ARM64Reg::INVALID_REG;
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m_gpr = nullptr;
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}
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Arm64Gen::ARM64Reg m_reg = Arm64Gen::ARM64Reg::INVALID_REG;
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Arm64RegCache* m_gpr = nullptr;
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};
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// Returns a temporary register
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// Unlocking is implicitly handled through RAII
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inline ScopedARM64Reg GetScopedReg() { return ScopedARM64Reg(*this); }
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void UpdateLastUsed(BitSet32 regs_used);
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// Get available host registers
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