JitIL: Modified psq_l implementation. Reverted psq_st. Removed compile warnings.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6114 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nodchip
parent
20704fca3d
commit
62c4d439ce
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@ -145,7 +145,6 @@ enum Opcode {
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StoreDouble,
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StoreFReg,
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FDCmpCR,
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CFloatOne, // Store 1.0f into the specified floating register
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// "Trinary" operators
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// FIXME: Need to change representation!
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@ -287,7 +286,7 @@ public:
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return FoldUOp(StoreGReg, value, reg);
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}
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InstLoc EmitNot(InstLoc op1) {
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return EmitXor(op1, EmitIntConst(-1U));
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return EmitXor(op1, EmitIntConst(0xFFFFFFFFU));
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}
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InstLoc EmitAnd(InstLoc op1, InstLoc op2) {
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return FoldBiOp(And, op1, op2);
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@ -517,9 +516,6 @@ public:
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InstLoc EmitFDCmpCR(InstLoc op1, InstLoc op2) {
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return FoldBiOp(FDCmpCR, op1, op2);
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}
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InstLoc EmitCFloatOne() {
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return FoldZeroOp(CFloatOne, 0);
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}
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InstLoc EmitLoadGQR(unsigned gqr) {
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return FoldZeroOp(LoadGQR, gqr);
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}
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@ -725,7 +725,6 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, bool UseProfile, bool Mak
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case LoadDouble:
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case LoadSingle:
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case LoadPaired:
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case CFloatOne:
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if (thisUsed)
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regMarkUse(RI, I, getOp1(I), 1);
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break;
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@ -1170,16 +1169,6 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, bool UseProfile, bool Mak
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regNormalRegClear(RI, I);
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break;
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}
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case CFloatOne: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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static const float one = 1.0f;
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Jit->MOV(32, R(ECX), Imm32(*(u32*)&one));
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Jit->MOVD_xmm(reg, R(ECX));
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RI.fregs[reg] = I;
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regNormalRegClear(RI, I);
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break;
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}
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case LoadDouble: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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@ -1200,9 +1189,12 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, bool UseProfile, bool Mak
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regSpill(RI, EAX);
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regSpill(RI, EDX);
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X64Reg reg = fregFindFreeReg(RI);
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unsigned int quantreg = *I >> 16;
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// The lower 3 bits is for GQR index. The next 1 bit is for inst.W
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unsigned int quantreg = (*I >> 16) & 0x7;
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unsigned int w = *I >> 19;
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Jit->MOVZX(32, 16, EAX, M(((char *)&GQR(quantreg)) + 2));
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Jit->MOVZX(32, 8, EDX, R(AL));
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Jit->OR(32, R(EDX), Imm8(w << 3));
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// FIXME: Fix ModR/M encoding to allow [EDX*4+disp32]! (MComplex can do this, no?)
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#ifdef _M_IX86
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Jit->SHL(32, R(EDX), Imm8(2));
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@ -38,6 +38,7 @@ void JitIL::psq_st(UGeckoInstruction inst)
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INSTRUCTION_START
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JITDISABLE(LoadStorePaired)
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if (js.memcheck) { Default(inst); return; }
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if (inst.W) {Default(inst); return;}
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IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_12), val;
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if (inst.RA)
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addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
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@ -45,14 +46,7 @@ void JitIL::psq_st(UGeckoInstruction inst)
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ibuild.EmitStoreGReg(addr, inst.RA);
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val = ibuild.EmitLoadFReg(inst.RS);
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val = ibuild.EmitCompactMRegToPacked(val);
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if (inst.W == 0) {
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ibuild.EmitStorePaired(val, addr, inst.I);
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} else {
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IREmitter::InstLoc addr4 = ibuild.EmitAdd(addr, ibuild.EmitIntConst(4));
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IREmitter::InstLoc backup = ibuild.EmitLoad32(addr4);
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ibuild.EmitStorePaired(val, addr, inst.I);
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ibuild.EmitStore32(backup, addr4);
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}
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}
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void JitIL::psq_l(UGeckoInstruction inst)
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@ -65,10 +59,7 @@ void JitIL::psq_l(UGeckoInstruction inst)
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addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
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if (inst.OPCD == 57)
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ibuild.EmitStoreGReg(addr, inst.RA);
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val = ibuild.EmitLoadPaired(addr, inst.I);
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if (inst.W) {
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val = ibuild.EmitFPMerge00(val, ibuild.EmitCFloatOne());
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}
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val = ibuild.EmitLoadPaired(addr, inst.I | (inst.W << 3)); // The lower 3 bits is for GQR index. The next 1 bit is for inst.W
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val = ibuild.EmitExpandPackedToMReg(val);
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ibuild.EmitStoreFReg(val, inst.RD);
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}
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@ -184,23 +184,23 @@ void JitIL::crXX(UGeckoInstruction inst)
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break;
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case 129:
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// crandc
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ecx = ibuild.EmitXor(ecx, ibuild.EmitIntConst(-1U));
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ecx = ibuild.EmitXor(ecx, ibuild.EmitIntConst(0xFFFFFFFFU));
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eax = ibuild.EmitAnd(eax, ecx);
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break;
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case 289:
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// creqv
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eax = ibuild.EmitXor(eax, ecx);
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eax = ibuild.EmitXor(eax, ibuild.EmitIntConst(-1U));
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eax = ibuild.EmitXor(eax, ibuild.EmitIntConst(0xFFFFFFFFU));
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break;
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case 225:
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// crnand
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eax = ibuild.EmitAnd(eax, ecx);
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eax = ibuild.EmitXor(eax, ibuild.EmitIntConst(-1U));
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eax = ibuild.EmitXor(eax, ibuild.EmitIntConst(0xFFFFFFFFU));
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break;
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case 33:
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// crnor
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eax = ibuild.EmitOr(eax, ecx);
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eax = ibuild.EmitXor(eax, ibuild.EmitIntConst(-1U));
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eax = ibuild.EmitXor(eax, ibuild.EmitIntConst(0xFFFFFFFFU));
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break;
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case 449:
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// cror
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@ -208,7 +208,7 @@ void JitIL::crXX(UGeckoInstruction inst)
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break;
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case 417:
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// crorc
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ecx = ibuild.EmitXor(ecx, ibuild.EmitIntConst(-1U));
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ecx = ibuild.EmitXor(ecx, ibuild.EmitIntConst(0xFFFFFFFFU));
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eax = ibuild.EmitOr(eax, ecx);
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break;
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case 193:
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@ -148,6 +148,7 @@ void CommonAsmRoutines::GenFifoXmm64Write()
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// Safe + Fast Quantizers, originally from JITIL by magumagu
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static const u8 GC_ALIGNED16(pbswapShuffle1x4[16]) = {3, 2, 1, 0, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
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static const u8 GC_ALIGNED16(pbswapShuffle2x4[16]) = {3, 2, 1, 0, 7, 6, 5, 4, 8, 9, 10, 11, 12, 13, 14, 15};
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static const float GC_ALIGNED16(m_quantizeTableS[]) =
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@ -199,6 +200,8 @@ static const float GC_ALIGNED16(m_255) = 255.0f;
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static const float GC_ALIGNED16(m_127) = 127.0f;
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static const float GC_ALIGNED16(m_m128) = -128.0f;
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static const float GC_ALIGNED16(m_one[]) = {1.0f, 0.0f, 0.0f, 0.0f};
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#define QUANTIZE_OVERFLOW_SAFE
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// according to Intel Docs CVTPS2DQ writes 0x80000000 if the source floating point value is out of int32 range
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@ -426,7 +429,8 @@ void CommonAsmRoutines::GenQuantizedSingleStores() {
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void CommonAsmRoutines::GenQuantizedLoads() {
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const u8* loadPairedIllegal = AlignCode4();
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UD2();
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const u8* loadPairedFloat = AlignCode4();
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const u8* loadPairedFloatTwo = AlignCode4();
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if (cpu_info.bSSSE3) {
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#ifdef _M_X64
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MOVQ_xmm(XMM0, MComplex(RBX, RCX, 1, 0));
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@ -465,7 +469,33 @@ void CommonAsmRoutines::GenQuantizedLoads() {
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}
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RET();
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const u8* loadPairedU8 = AlignCode4();
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const u8* loadPairedFloatOne = AlignCode4();
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if (cpu_info.bSSSE3) {
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#ifdef _M_X64
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MOVD_xmm(XMM0, MComplex(RBX, RCX, 1, 0));
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#else
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AND(32, R(ECX), Imm32(Memory::MEMVIEW32_MASK));
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MOVD_xmm(XMM0, MDisp(ECX, (u32)Memory::base));
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#endif
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PSHUFB(XMM0, M((void *)pbswapShuffle1x4));
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UNPCKLPS(XMM0, M((void*)m_one));
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} else {
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#ifdef _M_X64
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MOV(32, R(RCX), MComplex(RBX, RCX, 1, 0));
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BSWAP(32, RCX);
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MOVD_xmm(XMM0, R(RCX));
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UNPCKLPS(XMM0, M((void*)m_one));
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#else
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AND(32, R(ECX), Imm32(Memory::MEMVIEW32_MASK));
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MOV(32, R(EAX), MDisp(ECX, (u32)Memory::base));
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BSWAP(32, EAX);
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MOVD_xmm(XMM0, M(&psTemp[0]));
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UNPCKLPS(XMM0, M((void*)m_one));
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#endif
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}
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RET();
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const u8* loadPairedU8Two = AlignCode4();
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UnsafeLoadRegToRegNoSwap(ECX, ECX, 16, 0);
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MOVD_xmm(XMM0, R(ECX));
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PXOR(XMM1, R(XMM1));
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@ -478,7 +508,17 @@ void CommonAsmRoutines::GenQuantizedLoads() {
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MULPS(XMM0, R(XMM1));
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RET();
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const u8* loadPairedS8 = AlignCode4();
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const u8* loadPairedU8One = AlignCode4();
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UnsafeLoadRegToRegNoSwap(ECX, ECX, 8, 0); // ECX = 0x000000xx
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MOVD_xmm(XMM0, R(ECX));
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CVTDQ2PS(XMM0, R(XMM0)); // Is CVTSI2SS better?
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SHR(32, R(EAX), Imm8(6));
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MOVSS(XMM1, MDisp(EAX, (u32)(u64)m_dequantizeTableS));
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MULSS(XMM0, R(XMM1));
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UNPCKLPS(XMM0, M((void*)m_one));
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RET();
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const u8* loadPairedS8Two = AlignCode4();
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UnsafeLoadRegToRegNoSwap(ECX, ECX, 16, 0);
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MOVD_xmm(XMM0, R(ECX));
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PUNPCKLBW(XMM0, R(XMM0));
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@ -491,7 +531,19 @@ void CommonAsmRoutines::GenQuantizedLoads() {
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MULPS(XMM0, R(XMM1));
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RET();
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const u8* loadPairedU16 = AlignCode4();
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const u8* loadPairedS8One = AlignCode4();
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UnsafeLoadRegToRegNoSwap(ECX, ECX, 8, 0);
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SHL(32, R(ECX), Imm8(24));
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SAR(32, R(ECX), Imm8(24));
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MOVD_xmm(XMM0, R(ECX));
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CVTDQ2PS(XMM0, R(XMM0));
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SHR(32, R(EAX), Imm8(6));
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MOVSS(XMM1, MDisp(EAX, (u32)(u64)m_dequantizeTableS));
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MULSS(XMM0, R(XMM1));
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UNPCKLPS(XMM0, M((void*)m_one));
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RET();
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const u8* loadPairedU16Two = AlignCode4();
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UnsafeLoadRegToReg(ECX, ECX, 32, 0, false);
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ROL(32, R(ECX), Imm8(16));
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MOVD_xmm(XMM0, R(ECX));
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@ -504,7 +556,18 @@ void CommonAsmRoutines::GenQuantizedLoads() {
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MULPS(XMM0, R(XMM1));
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RET();
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const u8* loadPairedS16 = AlignCode4();
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const u8* loadPairedU16One = AlignCode4();
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UnsafeLoadRegToReg(ECX, ECX, 32, 0, false);
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SHR(32, R(ECX), Imm8(16));
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MOVD_xmm(XMM0, R(ECX));
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CVTDQ2PS(XMM0, R(XMM0));
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SHR(32, R(EAX), Imm8(6));
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MOVSS(XMM1, MDisp(EAX, (u32)(u64)m_dequantizeTableS));
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MULSS(XMM0, R(XMM1));
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UNPCKLPS(XMM0, M((void*)m_one));
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RET();
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const u8* loadPairedS16Two = AlignCode4();
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UnsafeLoadRegToReg(ECX, ECX, 32, 0, false);
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ROL(32, R(ECX), Imm8(16));
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MOVD_xmm(XMM0, R(ECX));
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@ -518,12 +581,33 @@ void CommonAsmRoutines::GenQuantizedLoads() {
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MULPS(XMM0, R(XMM1));
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RET();
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pairedLoadQuantized[0] = loadPairedFloat;
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const u8* loadPairedS16One = AlignCode4();
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UnsafeLoadRegToReg(ECX, ECX, 32, 0, false);
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SAR(32, R(ECX), Imm8(16));
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MOVD_xmm(XMM0, R(ECX));
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CVTDQ2PS(XMM0, R(XMM0));
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SHR(32, R(EAX), Imm8(6));
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AND(32, R(EAX), Imm32(0xFC));
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MOVSS(XMM1, MDisp(EAX, (u32)(u64)m_dequantizeTableS));
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MULSS(XMM0, R(XMM1));
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UNPCKLPS(XMM0, M((void*)m_one));
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RET();
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pairedLoadQuantized[0] = loadPairedFloatTwo;
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pairedLoadQuantized[1] = loadPairedIllegal;
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pairedLoadQuantized[2] = loadPairedIllegal;
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pairedLoadQuantized[3] = loadPairedIllegal;
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pairedLoadQuantized[4] = loadPairedU8;
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pairedLoadQuantized[5] = loadPairedU16;
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pairedLoadQuantized[6] = loadPairedS8;
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pairedLoadQuantized[7] = loadPairedS16;
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pairedLoadQuantized[4] = loadPairedU8Two;
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pairedLoadQuantized[5] = loadPairedU16Two;
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pairedLoadQuantized[6] = loadPairedS8Two;
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pairedLoadQuantized[7] = loadPairedS16Two;
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pairedLoadQuantized[8] = loadPairedFloatOne;
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pairedLoadQuantized[9] = loadPairedIllegal;
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pairedLoadQuantized[10] = loadPairedIllegal;
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pairedLoadQuantized[11] = loadPairedIllegal;
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pairedLoadQuantized[12] = loadPairedU8One;
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pairedLoadQuantized[13] = loadPairedU16One;
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pairedLoadQuantized[14] = loadPairedS8One;
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pairedLoadQuantized[15] = loadPairedS16One;
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}
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@ -56,7 +56,7 @@ public:
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// Out: XMM0: Bottom two 32-bit slots hold the read value,
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// converted to a pair of floats.
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// Trashes: EAX ECX EDX
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const u8 GC_ALIGNED16(*pairedLoadQuantized[8]);
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const u8 GC_ALIGNED16(*pairedLoadQuantized[16]);
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// In: array index: GQR to use.
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// In: ECX: Address to write to.
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