From 62adcaf5524dcff9bb6a5f23d99ba1b0a0e5b861 Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@Gmail.com>
Date: Fri, 12 Apr 2013 20:19:42 +0000
Subject: [PATCH] Fix fastmem on ARM

---
 Source/Core/Core/Src/PowerPC/JitArm32/JitArmCache.cpp    | 2 ++
 .../Core/Core/Src/PowerPC/JitArm32/JitArm_BackPatch.cpp  | 9 ++++-----
 .../Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp  | 2 +-
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArmCache.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArmCache.cpp
index 1706efafb0..82956364de 100644
--- a/Source/Core/Core/Src/PowerPC/JitArm32/JitArmCache.cpp
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitArmCache.cpp
@@ -33,6 +33,7 @@ using namespace ArmGen;
 	{
 		ARMXEmitter emit(location);
 		emit.B(address);
+		emit.FlushIcache();
 	}
 	void JitArmBlockCache::WriteDestroyBlock(const u8* location, u32 address)
 	{
@@ -41,6 +42,7 @@ using namespace ArmGen;
 		emit.MOVI2R(R12, (u32)jit->GetAsmRoutines()->dispatcher);
 		emit.STR(R11, R9, PPCSTATE_OFF(pc));
 		emit.B(R12);
+		emit.FlushIcache();
 	}
 
 
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_BackPatch.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_BackPatch.cpp
index 677dc238a8..2da8d9056b 100644
--- a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_BackPatch.cpp
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_BackPatch.cpp
@@ -50,33 +50,32 @@ static void BackPatchError(const std::string &text, u8 *codePtr, u32 emAddress)
 bool DisamLoadStore(const u32 inst, ARMReg &rD, u8 &accessSize, bool &Store)
 {
 	u8 op = (inst >> 20) & 0xFF;
-	printf("op: 0x%08x\n", op);
 	switch (op)
 	{
 		case 0x58: // STR
 		{
-			rD = (ARMReg)((inst >> 16) & 0xF);
+			rD = (ARMReg)((inst >> 12) & 0xF);
 			Store = true;
 			accessSize = 32;
 		}
 		break;
 		case 0x59: // LDR
 		{
-			rD = (ARMReg)((inst >> 16) & 0xF);
+			rD = (ARMReg)((inst >> 12) & 0xF);
 			Store = false;
 			accessSize = 32;
 		}
 		break;
 		case 0x05: // LDRH
 		{
-			rD = (ARMReg)((inst >> 16) & 0xF);
+			rD = (ARMReg)((inst >> 12) & 0xF);
 			Store = false;
 			accessSize = 16;
 		}
 		break;
 		case 0x45 + 0x18: // LDRB
 		{
-			rD = (ARMReg)((inst >> 16) & 0xF);
+			rD = (ARMReg)((inst >> 12) & 0xF);
 			Store = false;
 			accessSize  = 8;
 		}
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp
index 1617b0fef6..2ed961afb6 100644
--- a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp
@@ -34,7 +34,7 @@
 #ifdef ANDROID
 #define FASTMEM 0
 #else
-#define FASTMEM 0
+#define FASTMEM 1
 #endif
 void JitArm::stw(UGeckoInstruction inst)
 {