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Merge pull request #258 from Sonicadvance1/More-Fastmem 

[ARM] Implements more fastmem instructions in lXX.
This commit is contained in:
Ryan Houdek 2014-04-14 00:42:44 -05:00
parent a07f8fb65b 3f73fc37fc
commit 60202cff15
2 changed files with 22 additions and 5 deletions
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2
Source/Core/Core/PowerPC/JitArm32/Jit.h
View File

@ -108,7 +108,7 @@ public:
void UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 offset); void UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 offset);
void SafeStoreFromReg(bool fastmem, s32 dest, u32 value, s32 offsetReg, int accessSize, s32 offset); void SafeStoreFromReg(bool fastmem, s32 dest, u32 value, s32 offsetReg, int accessSize, s32 offset);
void UnsafeLoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offset); void UnsafeLoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offsetReg, s32 offset);
void SafeLoadToReg(bool fastmem, u32 dest, s32 addr, s32 offsetReg, int accessSize, s32 offset, bool signExtend, bool reverse); void SafeLoadToReg(bool fastmem, u32 dest, s32 addr, s32 offsetReg, int accessSize, s32 offset, bool signExtend, bool reverse);

25
Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStore.cpp
View File

@ -214,11 +214,20 @@ void JitArm::stX(UGeckoInstruction inst)
} }
} }
void JitArm::UnsafeLoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offset) void JitArm::UnsafeLoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offsetReg, s32 offset)
{ {
ARMReg rA = gpr.GetReg(); ARMReg rA = gpr.GetReg();
MOVI2R(rA, offset, false); // -3 if (offsetReg == -1)
ADD(addr, addr, rA); // - 1 {
MOVI2R(rA, offset, false); // -3
ADD(addr, addr, rA); // - 1
}
else
{
NOP(2); // -3, -2
// offsetReg is preloaded here
ADD(addr, addr, gpr.R(offsetReg)); // -1
}
// All this gets replaced on backpatch // All this gets replaced on backpatch
Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK) Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
@ -257,14 +266,19 @@ void JitArm::UnsafeLoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offse
void JitArm::SafeLoadToReg(bool fastmem, u32 dest, s32 addr, s32 offsetReg, int accessSize, s32 offset, bool signExtend, bool reverse) void JitArm::SafeLoadToReg(bool fastmem, u32 dest, s32 addr, s32 offsetReg, int accessSize, s32 offset, bool signExtend, bool reverse)
{ {
ARMReg RD = gpr.R(dest); ARMReg RD = gpr.R(dest);
if (Core::g_CoreStartupParameter.bFastmem && fastmem) if (Core::g_CoreStartupParameter.bFastmem && fastmem)
{ {
// Preload for fastmem
if (offsetReg != -1)
gpr.R(offsetReg);
if (addr != -1) if (addr != -1)
MOV(R10, gpr.R(addr)); MOV(R10, gpr.R(addr));
else else
MOV(R10, 0); MOV(R10, 0);
UnsafeLoadToReg(RD, R10, accessSize, offset); UnsafeLoadToReg(RD, R10, accessSize, offsetReg, offset);
return; return;
} }
ARMReg rA = gpr.GetReg(); ARMReg rA = gpr.GetReg();
@ -336,18 +350,21 @@ void JitArm::lXX(UGeckoInstruction inst)
case 55: // lwzux case 55: // lwzux
update = true; update = true;
case 23: // lwzx case 23: // lwzx
fastmem = true;
accessSize = 32; accessSize = 32;
offsetReg = b; offsetReg = b;
break; break;
case 119: //lbzux case 119: //lbzux
update = true; update = true;
case 87: // lbzx case 87: // lbzx
fastmem = true;
accessSize = 8; accessSize = 8;
offsetReg = b; offsetReg = b;
break; break;
case 311: // lhzux case 311: // lhzux
update = true; update = true;
case 279: // lhzx case 279: // lhzx
fastmem = true;
accessSize = 16; accessSize = 16;
offsetReg = b; offsetReg = b;
break; break;