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Merge pull request #9383 from lioncash/cr-fn 

DSP: Eliminate some magic values related to the CR register
This commit is contained in:
Léo Lam 2020-12-29 17:37:24 +01:00 committed by GitHub
parent 15d4ddf5da 64f93610ee
commit 5ff2cb9a74
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 11 additions and 9 deletions
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2
Source/Core/Core/DSP/DSPCore.cpp
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@ -157,7 +157,7 @@ bool SDSP::Initialize(const DSPInitOptions& opts)
r.sr |= SR_INT_ENABLE; r.sr |= SR_INT_ENABLE;
r.sr |= SR_EXT_INT_ENABLE; r.sr |= SR_EXT_INT_ENABLE;
cr = 0x804; cr = CR_INIT | CR_HALT;
InitializeIFX(); InitializeIFX();
// Mostly keep IRAM write protected. We unprotect only when DMA-ing // Mostly keep IRAM write protected. We unprotect only when DMA-ing
// in new ucodes. // in new ucodes.

4
Source/Core/Core/DSP/DSPCore.h
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@ -181,9 +181,11 @@ enum class StackRegister
// See HW/DSP.cpp. // See HW/DSP.cpp.
enum : u32 enum : u32
{ {
CR_RESET = 0x0001,
CR_EXTERNAL_INT = 0x0002, CR_EXTERNAL_INT = 0x0002,
CR_HALT = 0x0004, CR_HALT = 0x0004,
CR_INIT = 0x0400 CR_INIT_CODE = 0x0400,
CR_INIT = 0x0800
}; };
// SR bits // SR bits

2
Source/Core/Core/DSP/Interpreter/DSPIntBranch.cpp
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@ -122,7 +122,7 @@ void Interpreter::rti(const UDSPInstruction)
void Interpreter::halt(const UDSPInstruction) void Interpreter::halt(const UDSPInstruction)
{ {
auto& state = m_dsp_core.DSPState(); auto& state = m_dsp_core.DSPState();
state.cr |= 0x4; state.cr |= CR_HALT;
state.pc--; state.pc--;
} }

8
Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp
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@ -205,7 +205,7 @@ void Interpreter::WriteCR(u16 val)
{ {
INFO_LOG_FMT(DSPLLE, "DSP_CONTROL RESET"); INFO_LOG_FMT(DSPLLE, "DSP_CONTROL RESET");
m_dsp_core.Reset(); m_dsp_core.Reset();
val &= ~1; val &= ~CR_RESET;
} }
// init // init
else if (val == 4) else if (val == 4)
@ -214,7 +214,7 @@ void Interpreter::WriteCR(u16 val)
// OSInitAudioSystem ucode should send this mail - not DSP core itself // OSInitAudioSystem ucode should send this mail - not DSP core itself
INFO_LOG_FMT(DSPLLE, "DSP_CONTROL INIT"); INFO_LOG_FMT(DSPLLE, "DSP_CONTROL INIT");
m_dsp_core.SetInitHax(true); m_dsp_core.SetInitHax(true);
val |= 0x800; val |= CR_INIT;
} }
// update cr // update cr
@ -227,11 +227,11 @@ u16 Interpreter::ReadCR()
if ((state.pc & 0x8000) != 0) if ((state.pc & 0x8000) != 0)
{ {
state.cr |= 0x800; state.cr |= CR_INIT;
} }
else else
{ {
state.cr &= ~0x800; state.cr &= ~CR_INIT;
} }
return state.cr; return state.cr;

4
Source/Core/Core/DSP/Jit/x64/DSPJitBranch.cpp
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@ -273,9 +273,9 @@ void DSPEmitter::rti(const UDSPInstruction opc)
// HALT // HALT
// 0000 0000 0020 0001 // 0000 0000 0020 0001
// Stops execution of DSP code. Sets bit DSP_CR_HALT in register DREG_CR. // Stops execution of DSP code. Sets bit DSP_CR_HALT in register DREG_CR.
void DSPEmitter::halt(const UDSPInstruction opc) void DSPEmitter::halt(const UDSPInstruction)
{ {
OR(16, M_SDSP_cr(), Imm16(4)); OR(16, M_SDSP_cr(), Imm16(CR_HALT));
// g_dsp.pc = dsp_reg_load_stack(StackRegister::Call); // g_dsp.pc = dsp_reg_load_stack(StackRegister::Call);
dsp_reg_load_stack(StackRegister::Call); dsp_reg_load_stack(StackRegister::Call);
MOV(16, M_SDSP_pc(), R(DX)); MOV(16, M_SDSP_pc(), R(DX));