diff --git a/Source/Core/Core/DSP/DSPCore.cpp b/Source/Core/Core/DSP/DSPCore.cpp
index c58aeb0249..a12bee76c2 100644
--- a/Source/Core/Core/DSP/DSPCore.cpp
+++ b/Source/Core/Core/DSP/DSPCore.cpp
@@ -385,7 +385,7 @@ void SDSP::DoState(PointerWrap& p)
   }
 
   p.Do(step_counter);
-  p.DoArray(ifx_regs);
+  p.DoArray(m_ifx_regs);
   m_accelerator->DoState(p);
   p.Do(m_mailbox[0]);
   p.Do(m_mailbox[1]);
diff --git a/Source/Core/Core/DSP/DSPCore.h b/Source/Core/Core/DSP/DSPCore.h
index 504890dcb5..e2f43f391c 100644
--- a/Source/Core/Core/DSP/DSPCore.h
+++ b/Source/Core/Core/DSP/DSPCore.h
@@ -429,9 +429,6 @@ struct SDSP
   u32 iram_crc = 0;
   u64 step_counter = 0;
 
-  // Accelerator / DMA / other hardware registers. Not GPRs.
-  std::array<u16, 256> ifx_regs{};
-
   // When state saving, all of the above can just be memcpy'd into the save state.
   // The below needs special handling.
   u16* iram = nullptr;
@@ -453,6 +450,9 @@ private:
 
   u16 ReadIFXImpl(u16 address);
 
+  // Accelerator / DMA / other hardware registers. Not GPRs.
+  std::array<u16, 256> m_ifx_regs{};
+
   std::unique_ptr<Accelerator> m_accelerator;
   std::array<std::atomic<u32>, 2> m_mailbox;
   DSPCore& m_dsp_core;
diff --git a/Source/Core/Core/DSP/DSPHWInterface.cpp b/Source/Core/Core/DSP/DSPHWInterface.cpp
index c0c2e0c36e..f182d7460f 100644
--- a/Source/Core/Core/DSP/DSPHWInterface.cpp
+++ b/Source/Core/Core/DSP/DSPHWInterface.cpp
@@ -23,7 +23,7 @@ namespace DSP
 {
 void SDSP::InitializeIFX()
 {
-  ifx_regs.fill(0);
+  m_ifx_regs.fill(0);
 
   GetMailbox(Mailbox::CPU).store(0);
   GetMailbox(Mailbox::DSP).store(0);
@@ -118,14 +118,14 @@ void SDSP::WriteIFX(u32 address, u16 value)
     break;
 
   case DSP_DSBL:
-    ifx_regs[DSP_DSBL] = value;
-    ifx_regs[DSP_DSCR] |= 4;  // Doesn't really matter since we do DMA instantly
-    if (!ifx_regs[DSP_AMDM])
+    m_ifx_regs[DSP_DSBL] = value;
+    m_ifx_regs[DSP_DSCR] |= 4;  // Doesn't really matter since we do DMA instantly
+    if (!m_ifx_regs[DSP_AMDM])
       DoDMA();
     else
       NOTICE_LOG_FMT(DSPLLE, "Masked DMA skipped");
-    ifx_regs[DSP_DSCR] &= ~4;
-    ifx_regs[DSP_DSBL] = 0;
+    m_ifx_regs[DSP_DSCR] &= ~4;
+    m_ifx_regs[DSP_DSBL] = 0;
     break;
 
   case DSP_GAIN:
@@ -138,7 +138,7 @@ void SDSP::WriteIFX(u32 address, u16 value)
   case DSP_DSMAH:
   case DSP_DSMAL:
   case DSP_DSCR:
-    ifx_regs[address & 0xFF] = value;
+    m_ifx_regs[address & 0xFF] = value;
     break;
 
   case DSP_ACSAH:
@@ -199,7 +199,7 @@ void SDSP::WriteIFX(u32 address, u16 value)
     {
       ERROR_LOG_FMT(DSPLLE, "{:04x} MW {:04x} ({:04x})", pc, address, value);
     }
-    ifx_regs[address & 0xFF] = value;
+    m_ifx_regs[address & 0xFF] = value;
     break;
   }
 }
@@ -221,7 +221,7 @@ u16 SDSP::ReadIFXImpl(u16 address)
     return ReadMailboxLow(Mailbox::CPU);
 
   case DSP_DSCR:
-    return ifx_regs[address & 0xFF];
+    return m_ifx_regs[address & 0xFF];
 
   case DSP_ACSAH:
     return static_cast<u16>(m_accelerator->GetStartAddress() >> 16);
@@ -244,13 +244,13 @@ u16 SDSP::ReadIFXImpl(u16 address)
   case DSP_PRED_SCALE:
     return m_accelerator->GetPredScale();
   case DSP_ACCELERATOR:  // ADPCM Accelerator reads
-    return m_accelerator->Read(reinterpret_cast<s16*>(&ifx_regs[DSP_COEF_A1_0]));
+    return m_accelerator->Read(reinterpret_cast<s16*>(&m_ifx_regs[DSP_COEF_A1_0]));
   case DSP_ACDATA1:  // Accelerator reads (Zelda type) - "UnkZelda"
     return m_accelerator->ReadD3();
 
   default:
   {
-    const u16 ifx_reg = ifx_regs[address & 0xFF];
+    const u16 ifx_reg = m_ifx_regs[address & 0xFF];
 
     if ((address & 0xff) >= 0xa0)
     {
@@ -323,10 +323,10 @@ const u8* SDSP::DDMAOut(u16 dsp_addr, u32 addr, u32 size)
 
 void SDSP::DoDMA()
 {
-  const u32 addr = (ifx_regs[DSP_DSMAH] << 16) | ifx_regs[DSP_DSMAL];
-  const u16 ctl = ifx_regs[DSP_DSCR];
-  const u16 dsp_addr = ifx_regs[DSP_DSPA] * 2;
-  const u16 len = ifx_regs[DSP_DSBL];
+  const u32 addr = (m_ifx_regs[DSP_DSMAH] << 16) | m_ifx_regs[DSP_DSMAL];
+  const u16 ctl = m_ifx_regs[DSP_DSCR];
+  const u16 dsp_addr = m_ifx_regs[DSP_DSPA] * 2;
+  const u16 len = m_ifx_regs[DSP_DSBL];
 
   if (len > 0x4000)
   {