Merge pull request #7138 from lioncash/dsp-table
DSPTables: Separate interpreter and JIT functions from main info table
This commit is contained in:
commit
5f7dc31a9f
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@ -58,6 +58,7 @@ add_library(core
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DSP/Interpreter/DSPIntLoadStore.cpp
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DSP/Interpreter/DSPIntMisc.cpp
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DSP/Interpreter/DSPIntMultiplier.cpp
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DSP/Interpreter/DSPIntTables.cpp
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DSP/Jit/x64/DSPEmitter.cpp
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DSP/Jit/x64/DSPJitRegCache.cpp
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DSP/Jit/x64/DSPJitExtOps.cpp
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@ -65,9 +66,10 @@ add_library(core
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DSP/Jit/x64/DSPJitCCUtil.cpp
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DSP/Jit/x64/DSPJitArithmetic.cpp
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DSP/Jit/x64/DSPJitLoadStore.cpp
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DSP/Jit/x64/DSPJitMultiplier.cpp
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DSP/Jit/x64/DSPJitUtil.cpp
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DSP/Jit/x64/DSPJitMisc.cpp
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DSP/Jit/x64/DSPJitMultiplier.cpp
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DSP/Jit/x64/DSPJitTables.cpp
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DSP/Jit/x64/DSPJitUtil.cpp
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FifoPlayer/FifoAnalyzer.cpp
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FifoPlayer/FifoDataFile.cpp
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FifoPlayer/FifoPlaybackAnalyzer.cpp
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@ -81,6 +81,7 @@
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<ClCompile Include="DSP\Interpreter\DSPIntLoadStore.cpp" />
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<ClCompile Include="DSP\Interpreter\DSPIntMisc.cpp" />
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<ClCompile Include="DSP\Interpreter\DSPIntMultiplier.cpp" />
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<ClCompile Include="DSP\Interpreter\DSPIntTables.cpp" />
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<ClCompile Include="DSP\Jit\x64\DSPEmitter.cpp" />
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<ClCompile Include="DSP\Jit\x64\DSPJitArithmetic.cpp" />
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<ClCompile Include="DSP\Jit\x64\DSPJitBranch.cpp" />
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@ -90,6 +91,7 @@
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<ClCompile Include="DSP\Jit\x64\DSPJitMisc.cpp" />
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<ClCompile Include="DSP\Jit\x64\DSPJitMultiplier.cpp" />
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<ClCompile Include="DSP\Jit\x64\DSPJitRegCache.cpp" />
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<ClCompile Include="DSP\Jit\x64\DSPJitTables.cpp" />
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<ClCompile Include="DSP\Jit\x64\DSPJitUtil.cpp" />
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<ClCompile Include="DSP\LabelMap.cpp" />
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<ClCompile Include="FifoPlayer\FifoAnalyzer.cpp" />
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@ -341,9 +343,11 @@
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<ClInclude Include="DSP\Interpreter\DSPIntCCUtil.h" />
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<ClInclude Include="DSP\Interpreter\DSPInterpreter.h" />
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<ClInclude Include="DSP\Interpreter\DSPIntExtOps.h" />
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<ClInclude Include="DSP\Interpreter\DSPIntTables.h" />
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<ClInclude Include="DSP\Interpreter\DSPIntUtil.h" />
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<ClInclude Include="DSP\Jit\x64\DSPEmitter.h" />
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<ClInclude Include="DSP\Jit\x64\DSPJitRegCache.h" />
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<ClInclude Include="DSP\Jit\x64\DSPJitTables.h" />
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<ClInclude Include="DSP\LabelMap.h" />
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<ClInclude Include="FifoPlayer\FifoAnalyzer.h" />
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<ClInclude Include="FifoPlayer\FifoDataFile.h" />
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@ -240,6 +240,9 @@
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<ClCompile Include="DSP\Interpreter\DSPIntMultiplier.cpp">
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<Filter>DSPCore\Interpreter</Filter>
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</ClCompile>
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<ClCompile Include="DSP\Interpreter\DSPIntTables.cpp">
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<Filter>DSPCore\Interpreter</Filter>
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</ClCompile>
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<ClCompile Include="DSP\Jit\x64\DSPJitRegCache.cpp">
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<Filter>DSPCore\Jit\x64</Filter>
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</ClCompile>
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@ -267,6 +270,9 @@
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<ClCompile Include="DSP\Jit\x64\DSPEmitter.cpp">
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<Filter>DSPCore\Jit\x64</Filter>
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</ClCompile>
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<ClCompile Include="DSP\Jit\x64\DSPJitTables.cpp">
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<Filter>DSPCore\Jit\x64</Filter>
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</ClCompile>
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<ClCompile Include="DSP\Jit\x64\DSPJitUtil.cpp">
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<Filter>DSPCore\Jit\x64</Filter>
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</ClCompile>
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@ -960,12 +966,18 @@
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<ClInclude Include="DSP\Interpreter\DSPIntExtOps.h">
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<Filter>DSPCore\Interpreter</Filter>
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</ClInclude>
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<ClInclude Include="DSP\Interpreter\DSPIntTables.h">
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<Filter>DSPCore\Interpreter</Filter>
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</ClInclude>
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<ClInclude Include="DSP\Interpreter\DSPIntUtil.h">
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<Filter>DSPCore\Interpreter</Filter>
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</ClInclude>
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<ClInclude Include="DSP\Jit\x64\DSPJitRegCache.h">
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<Filter>DSPCore\Jit\x64</Filter>
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</ClInclude>
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<ClInclude Include="DSP\Jit\x64\DSPJitTables.h">
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<Filter>DSPCore\Jit\x64</Filter>
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</ClInclude>
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<ClInclude Include="DSP\Jit\x64\DSPEmitter.h">
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<Filter>DSPCore\Jit\x64</Filter>
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</ClInclude>
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@ -12,6 +12,7 @@
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#include "Common/CommonTypes.h"
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#include "Common/File.h"
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#include "Common/FileUtil.h"
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#include "Common/MsgHandler.h"
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#include "Common/StringUtil.h"
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#include "Common/Swap.h"
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@ -11,6 +11,7 @@
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#include <vector>
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#include "Common/CommonTypes.h"
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#include "Common/Logging/Log.h"
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#include "Common/StringUtil.h"
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#include "Core/DSP/DSPTables.h"
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@ -144,8 +145,7 @@ bool DSPDisassembler::DisassembleOpcode(const u16* binbuf, u16* pc, std::string&
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// Find main opcode
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const DSPOPCTemplate* opc = FindOpInfoByOpcode(op1);
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const DSPOPCTemplate fake_op = {
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"CW", 0x0000, 0x0000, nullptr, nullptr, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}},
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const DSPOPCTemplate fake_op = {"CW", 0x0000, 0x0000, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}},
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false, false, false, false, false};
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if (!opc)
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opc = &fake_op;
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@ -11,325 +11,321 @@
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#include <cstddef>
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#include "Common/CommonTypes.h"
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#include "Common/Logging/Log.h"
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#include "Core/DSP/Interpreter/DSPIntExtOps.h"
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#include "Core/DSP/Interpreter/DSPInterpreter.h"
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#include "Core/DSP/Jit/x64/DSPEmitter.h"
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#include "Core/DSP/Interpreter/DSPIntTables.h"
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namespace DSP
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{
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using JIT::x64::DSPEmitter;
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// clang-format off
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const std::array<DSPOPCTemplate, 214> s_opcodes =
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{{
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// # of parameters----+ {type, size, loc, lshift, mask} branch reads PC // instruction approximation
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// name opcode mask interpreter function JIT function size-V V param 1 param 2 param 3 extendable uncond. updates SR
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{"NOP", 0x0000, 0xfffc, Interpreter::nop, &DSPEmitter::nop, 1, 0, {}, false, false, false, false, false}, // no operation
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// name opcode mask size-V V param 1 param 2 param 3 extendable uncond. updates SR
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{"NOP", 0x0000, 0xfffc, 1, 0, {}, false, false, false, false, false}, // no operation
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{"DAR", 0x0004, 0xfffc, Interpreter::dar, &DSPEmitter::dar, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arD--
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{"IAR", 0x0008, 0xfffc, Interpreter::iar, &DSPEmitter::iar, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arD++
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{"SUBARN", 0x000c, 0xfffc, Interpreter::subarn, &DSPEmitter::subarn, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arD -= $ixS
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{"ADDARN", 0x0010, 0xfff0, Interpreter::addarn, &DSPEmitter::addarn, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, false, false, false, false, false}, // $arD += $ixS
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{"DAR", 0x0004, 0xfffc, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arD--
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{"IAR", 0x0008, 0xfffc, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arD++
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{"SUBARN", 0x000c, 0xfffc, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arD -= $ixS
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{"ADDARN", 0x0010, 0xfff0, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, false, false, false, false, false}, // $arD += $ixS
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{"HALT", 0x0021, 0xffff, Interpreter::halt, &DSPEmitter::halt, 1, 0, {}, false, true, true, false, false}, // halt until reset
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{"HALT", 0x0021, 0xffff, 1, 0, {}, false, true, true, false, false}, // halt until reset
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{"RETGE", 0x02d0, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, false, true, false}, // return if greater or equal
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{"RETL", 0x02d1, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, false, true, false}, // return if less
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{"RETG", 0x02d2, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, false, true, false}, // return if greater
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{"RETLE", 0x02d3, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, false, true, false}, // return if less or equal
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{"RETNZ", 0x02d4, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, false, true, false}, // return if not zero
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{"RETZ", 0x02d5, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, false, true, false}, // return if zero
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{"RETNC", 0x02d6, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, false, true, false}, // return if not carry
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{"RETC", 0x02d7, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, false, true, false}, // return if carry
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{"RETx8", 0x02d8, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, false, true, false}, // return if TODO
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{"RETx9", 0x02d9, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, false, true, false}, // return if TODO
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{"RETxA", 0x02da, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, false, true, false}, // return if TODO
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{"RETxB", 0x02db, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, false, true, false}, // return if TODO
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{"RETLNZ", 0x02dc, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, false, true, false}, // return if logic not zero
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{"RETLZ", 0x02dd, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, false, true, false}, // return if logic zero
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{"RETO", 0x02de, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, false, true, false}, // return if overflow
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{"RET", 0x02df, 0xffff, Interpreter::ret, &DSPEmitter::ret, 1, 0, {}, false, true, true, false, false}, // unconditional return
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{"RETGE", 0x02d0, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if greater or equal
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{"RETL", 0x02d1, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if less
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{"RETG", 0x02d2, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if greater
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{"RETLE", 0x02d3, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if less or equal
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{"RETNZ", 0x02d4, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if not zero
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{"RETZ", 0x02d5, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if zero
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{"RETNC", 0x02d6, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if not carry
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{"RETC", 0x02d7, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if carry
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{"RETx8", 0x02d8, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if TODO
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{"RETx9", 0x02d9, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if TODO
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{"RETxA", 0x02da, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if TODO
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{"RETxB", 0x02db, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if TODO
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{"RETLNZ", 0x02dc, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if logic not zero
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{"RETLZ", 0x02dd, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if logic zero
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{"RETO", 0x02de, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if overflow
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{"RET", 0x02df, 0xffff, 1, 0, {}, false, true, true, false, false}, // unconditional return
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{"RTI", 0x02ff, 0xffff, Interpreter::rti, &DSPEmitter::rti, 1, 0, {}, false, true, true, false, false}, // return from interrupt
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{"RTI", 0x02ff, 0xffff, 1, 0, {}, false, true, true, false, false}, // return from interrupt
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{"CALLGE", 0x02b0, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if greater or equal
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{"CALLL", 0x02b1, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if less
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{"CALLG", 0x02b2, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if greater
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{"CALLLE", 0x02b3, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if less or equal
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{"CALLNZ", 0x02b4, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if not zero
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{"CALLZ", 0x02b5, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if zero
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{"CALLNC", 0x02b6, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if not carry
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{"CALLC", 0x02b7, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if carry
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{"CALLx8", 0x02b8, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if TODO
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{"CALLx9", 0x02b9, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if TODO
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{"CALLxA", 0x02ba, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if TODO
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{"CALLxB", 0x02bb, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if TODO
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{"CALLLNZ", 0x02bc, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if logic not zero
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{"CALLLZ", 0x02bd, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if logic zero
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{"CALLO", 0x02be, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if overflow
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{"CALL", 0x02bf, 0xffff, Interpreter::call, &DSPEmitter::call, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true, false}, // unconditional call
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{"CALLGE", 0x02b0, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if greater or equal
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{"CALLL", 0x02b1, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if less
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{"CALLG", 0x02b2, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if greater
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{"CALLLE", 0x02b3, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if less or equal
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{"CALLNZ", 0x02b4, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if not zero
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{"CALLZ", 0x02b5, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if zero
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{"CALLNC", 0x02b6, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if not carry
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{"CALLC", 0x02b7, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if carry
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{"CALLx8", 0x02b8, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if TODO
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{"CALLx9", 0x02b9, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if TODO
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{"CALLxA", 0x02ba, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if TODO
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{"CALLxB", 0x02bb, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if TODO
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{"CALLLNZ", 0x02bc, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if logic not zero
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{"CALLLZ", 0x02bd, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if logic zero
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{"CALLO", 0x02be, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if overflow
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{"CALL", 0x02bf, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true, false}, // unconditional call
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{"IFGE", 0x0270, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, false, true, false}, // if greater or equal
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{"IFL", 0x0271, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, false, true, false}, // if less
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{"IFG", 0x0272, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, false, true, false}, // if greater
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{"IFLE", 0x0273, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, false, true, false}, // if less or equal
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{"IFNZ", 0x0274, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, false, true, false}, // if not zero
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{"IFZ", 0x0275, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, false, true, false}, // if zero
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{"IFNC", 0x0276, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, false, true, false}, // if not carry
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{"IFC", 0x0277, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, false, true, false}, // if carry
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{"IFx8", 0x0278, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, false, true, false}, // if TODO
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{"IFx9", 0x0279, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, false, true, false}, // if TODO
|
||||
{"IFxA", 0x027a, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, false, true, false}, // if TODO
|
||||
{"IFxB", 0x027b, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, false, true, false}, // if TODO
|
||||
{"IFLNZ", 0x027c, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, false, true, false}, // if logic not zero
|
||||
{"IFLZ", 0x027d, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, false, true, false}, // if logic zero
|
||||
{"IFO", 0x027e, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, false, true, false}, // if overflow
|
||||
{"IF", 0x027f, 0xffff, Interpreter::ifcc, &DSPEmitter::ifcc, 1, 0, {}, false, true, true, true, false}, // what is this, I don't even...
|
||||
{"IFGE", 0x0270, 0xffff, 1, 0, {}, false, true, false, true, false}, // if greater or equal
|
||||
{"IFL", 0x0271, 0xffff, 1, 0, {}, false, true, false, true, false}, // if less
|
||||
{"IFG", 0x0272, 0xffff, 1, 0, {}, false, true, false, true, false}, // if greater
|
||||
{"IFLE", 0x0273, 0xffff, 1, 0, {}, false, true, false, true, false}, // if less or equal
|
||||
{"IFNZ", 0x0274, 0xffff, 1, 0, {}, false, true, false, true, false}, // if not zero
|
||||
{"IFZ", 0x0275, 0xffff, 1, 0, {}, false, true, false, true, false}, // if zero
|
||||
{"IFNC", 0x0276, 0xffff, 1, 0, {}, false, true, false, true, false}, // if not carry
|
||||
{"IFC", 0x0277, 0xffff, 1, 0, {}, false, true, false, true, false}, // if carry
|
||||
{"IFx8", 0x0278, 0xffff, 1, 0, {}, false, true, false, true, false}, // if TODO
|
||||
{"IFx9", 0x0279, 0xffff, 1, 0, {}, false, true, false, true, false}, // if TODO
|
||||
{"IFxA", 0x027a, 0xffff, 1, 0, {}, false, true, false, true, false}, // if TODO
|
||||
{"IFxB", 0x027b, 0xffff, 1, 0, {}, false, true, false, true, false}, // if TODO
|
||||
{"IFLNZ", 0x027c, 0xffff, 1, 0, {}, false, true, false, true, false}, // if logic not zero
|
||||
{"IFLZ", 0x027d, 0xffff, 1, 0, {}, false, true, false, true, false}, // if logic zero
|
||||
{"IFO", 0x027e, 0xffff, 1, 0, {}, false, true, false, true, false}, // if overflow
|
||||
{"IF", 0x027f, 0xffff, 1, 0, {}, false, true, true, true, false}, // what is this, I don't even...
|
||||
|
||||
{"JGE", 0x0290, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if greater or equal
|
||||
{"JL", 0x0291, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if less
|
||||
{"JG", 0x0292, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if greater
|
||||
{"JLE", 0x0293, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if less or equal
|
||||
{"JNZ", 0x0294, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if not zero
|
||||
{"JZ", 0x0295, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if zero
|
||||
{"JNC", 0x0296, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if not carry
|
||||
{"JC", 0x0297, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if carry
|
||||
{"JMPx8", 0x0298, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if TODO
|
||||
{"JMPx9", 0x0299, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if TODO
|
||||
{"JMPxA", 0x029a, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if TODO
|
||||
{"JMPxB", 0x029b, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if TODO
|
||||
{"JLNZ", 0x029c, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if logic not zero
|
||||
{"JLZ", 0x029d, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if logic zero
|
||||
{"JO", 0x029e, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if overflow
|
||||
{"JMP", 0x029f, 0xffff, Interpreter::jcc, &DSPEmitter::jcc, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true, false}, // unconditional jump
|
||||
{"JGE", 0x0290, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if greater or equal
|
||||
{"JL", 0x0291, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if less
|
||||
{"JG", 0x0292, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if greater
|
||||
{"JLE", 0x0293, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if less or equal
|
||||
{"JNZ", 0x0294, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if not zero
|
||||
{"JZ", 0x0295, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if zero
|
||||
{"JNC", 0x0296, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if not carry
|
||||
{"JC", 0x0297, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if carry
|
||||
{"JMPx8", 0x0298, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if TODO
|
||||
{"JMPx9", 0x0299, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if TODO
|
||||
{"JMPxA", 0x029a, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if TODO
|
||||
{"JMPxB", 0x029b, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if TODO
|
||||
{"JLNZ", 0x029c, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if logic not zero
|
||||
{"JLZ", 0x029d, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if logic zero
|
||||
{"JO", 0x029e, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if overflow
|
||||
{"JMP", 0x029f, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true, false}, // unconditional jump
|
||||
|
||||
{"JRGE", 0x1700, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if greater or equal
|
||||
{"JRL", 0x1701, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if less
|
||||
{"JRG", 0x1702, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if greater
|
||||
{"JRLE", 0x1703, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if less or equal
|
||||
{"JRNZ", 0x1704, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if not zero
|
||||
{"JRZ", 0x1705, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if zero
|
||||
{"JRNC", 0x1706, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if not carry
|
||||
{"JRC", 0x1707, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if carry
|
||||
{"JMPRx8", 0x1708, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if TODO
|
||||
{"JMPRx9", 0x1709, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if TODO
|
||||
{"JMPRxA", 0x170a, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if TODO
|
||||
{"JMPRxB", 0x170b, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if TODO
|
||||
{"JRLNZ", 0x170c, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if logic not zero
|
||||
{"JRLZ", 0x170d, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if logic zero
|
||||
{"JRO", 0x170e, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if overflow
|
||||
{"JMPR", 0x170f, 0xff1f, Interpreter::jmprcc, &DSPEmitter::jmprcc, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, true, false, false}, // jump to $R
|
||||
{"JRGE", 0x1700, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if greater or equal
|
||||
{"JRL", 0x1701, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if less
|
||||
{"JRG", 0x1702, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if greater
|
||||
{"JRLE", 0x1703, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if less or equal
|
||||
{"JRNZ", 0x1704, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if not zero
|
||||
{"JRZ", 0x1705, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if zero
|
||||
{"JRNC", 0x1706, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if not carry
|
||||
{"JRC", 0x1707, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if carry
|
||||
{"JMPRx8", 0x1708, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if TODO
|
||||
{"JMPRx9", 0x1709, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if TODO
|
||||
{"JMPRxA", 0x170a, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if TODO
|
||||
{"JMPRxB", 0x170b, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if TODO
|
||||
{"JRLNZ", 0x170c, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if logic not zero
|
||||
{"JRLZ", 0x170d, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if logic zero
|
||||
{"JRO", 0x170e, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if overflow
|
||||
{"JMPR", 0x170f, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, true, false, false}, // jump to $R
|
||||
|
||||
{"CALLRGE", 0x1710, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if greater or equal
|
||||
{"CALLRL", 0x1711, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if less
|
||||
{"CALLRG", 0x1712, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if greater
|
||||
{"CALLRLE", 0x1713, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if less or equal
|
||||
{"CALLRNZ", 0x1714, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if not zero
|
||||
{"CALLRZ", 0x1715, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if zero
|
||||
{"CALLRNC", 0x1716, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if not carry
|
||||
{"CALLRC", 0x1717, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if carry
|
||||
{"CALLRx8", 0x1718, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if TODO
|
||||
{"CALLRx9", 0x1719, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if TODO
|
||||
{"CALLRxA", 0x171a, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if TODO
|
||||
{"CALLRxB", 0x171b, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if TODO
|
||||
{"CALLRLNZ", 0x171c, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if logic not zero
|
||||
{"CALLRLZ", 0x171d, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if logic zero
|
||||
{"CALLRO", 0x171e, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if overflow
|
||||
{"CALLR", 0x171f, 0xff1f, Interpreter::callr, &DSPEmitter::callr, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, true, true, false}, // call $R
|
||||
{"CALLRGE", 0x1710, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if greater or equal
|
||||
{"CALLRL", 0x1711, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if less
|
||||
{"CALLRG", 0x1712, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if greater
|
||||
{"CALLRLE", 0x1713, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if less or equal
|
||||
{"CALLRNZ", 0x1714, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if not zero
|
||||
{"CALLRZ", 0x1715, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if zero
|
||||
{"CALLRNC", 0x1716, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if not carry
|
||||
{"CALLRC", 0x1717, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if carry
|
||||
{"CALLRx8", 0x1718, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if TODO
|
||||
{"CALLRx9", 0x1719, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if TODO
|
||||
{"CALLRxA", 0x171a, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if TODO
|
||||
{"CALLRxB", 0x171b, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if TODO
|
||||
{"CALLRLNZ", 0x171c, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if logic not zero
|
||||
{"CALLRLZ", 0x171d, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if logic zero
|
||||
{"CALLRO", 0x171e, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if overflow
|
||||
{"CALLR", 0x171f, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, true, true, false}, // call $R
|
||||
|
||||
{"SBCLR", 0x1200, 0xff00, Interpreter::sbclr, &DSPEmitter::sbclr, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false, false, false, false}, // $sr &= ~(I + 6)
|
||||
{"SBSET", 0x1300, 0xff00, Interpreter::sbset, &DSPEmitter::sbset, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false, false, false, false}, // $sr |= (I + 6)
|
||||
{"SBCLR", 0x1200, 0xff00, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false, false, false, false}, // $sr &= ~(I + 6)
|
||||
{"SBSET", 0x1300, 0xff00, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false, false, false, false}, // $sr |= (I + 6)
|
||||
|
||||
{"LSL", 0x1400, 0xfec0, Interpreter::lsl, &DSPEmitter::lsl, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, // $acR <<= I
|
||||
{"LSR", 0x1440, 0xfec0, Interpreter::lsr, &DSPEmitter::lsr, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, // $acR >>= I (shifting in zeros)
|
||||
{"ASL", 0x1480, 0xfec0, Interpreter::asl, &DSPEmitter::asl, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, // $acR <<= I
|
||||
{"ASR", 0x14c0, 0xfec0, Interpreter::asr, &DSPEmitter::asr, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, // $acR >>= I (shifting in sign bits)
|
||||
{"LSL", 0x1400, 0xfec0, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, // $acR <<= I
|
||||
{"LSR", 0x1440, 0xfec0, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, // $acR >>= I (shifting in zeros)
|
||||
{"ASL", 0x1480, 0xfec0, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, // $acR <<= I
|
||||
{"ASR", 0x14c0, 0xfec0, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, // $acR >>= I (shifting in sign bits)
|
||||
|
||||
// these two were discovered by ector
|
||||
{"LSRN", 0x02ca, 0xffff, Interpreter::lsrn, &DSPEmitter::lsrn, 1, 0, {}, false, false, false, false, true}, // $ac0 >>=/<<= $ac1.m[0-6]
|
||||
{"ASRN", 0x02cb, 0xffff, Interpreter::asrn, &DSPEmitter::asrn, 1, 0, {}, false, false, false, false, true}, // $ac0 >>=/<<= $ac1.m[0-6] (arithmetic)
|
||||
{"LSRN", 0x02ca, 0xffff, 1, 0, {}, false, false, false, false, true}, // $ac0 >>=/<<= $ac1.m[0-6]
|
||||
{"ASRN", 0x02cb, 0xffff, 1, 0, {}, false, false, false, false, true}, // $ac0 >>=/<<= $ac1.m[0-6] (arithmetic)
|
||||
|
||||
{"LRI", 0x0080, 0xffe0, Interpreter::lri, &DSPEmitter::lri, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, false}, // $D = I
|
||||
{"LR", 0x00c0, 0xffe0, Interpreter::lr, &DSPEmitter::lr, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_MEM, 2, 1, 0, 0xffff}}, false, false, false, true, false}, // $D = MEM[M]
|
||||
{"SR", 0x00e0, 0xffe0, Interpreter::sr, &DSPEmitter::sr, 2, 2, {{P_MEM, 2, 1, 0, 0xffff}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, true, false}, // MEM[M] = $S
|
||||
{"LRI", 0x0080, 0xffe0, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, false}, // $D = I
|
||||
{"LR", 0x00c0, 0xffe0, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_MEM, 2, 1, 0, 0xffff}}, false, false, false, true, false}, // $D = MEM[M]
|
||||
{"SR", 0x00e0, 0xffe0, 2, 2, {{P_MEM, 2, 1, 0, 0xffff}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, true, false}, // MEM[M] = $S
|
||||
|
||||
{"MRR", 0x1c00, 0xfc00, Interpreter::mrr, &DSPEmitter::mrr, 1, 2, {{P_REG, 1, 0, 5, 0x03e0}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, // $D = $S
|
||||
{"MRR", 0x1c00, 0xfc00, 1, 2, {{P_REG, 1, 0, 5, 0x03e0}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, // $D = $S
|
||||
|
||||
{"SI", 0x1600, 0xff00, Interpreter::si, &DSPEmitter::si, 2, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, false}, // MEM[M] = I
|
||||
{"SI", 0x1600, 0xff00, 2, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, false}, // MEM[M] = I
|
||||
|
||||
{"ADDIS", 0x0400, 0xfe00, Interpreter::addis, &DSPEmitter::addis, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false, false, true}, // $acD.hm += I
|
||||
{"CMPIS", 0x0600, 0xfe00, Interpreter::cmpis, &DSPEmitter::cmpis, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false, false, true}, // FLAGS($acD - I)
|
||||
{"LRIS", 0x0800, 0xf800, Interpreter::lris, &DSPEmitter::lris, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false, false, true}, // $(D+24) = I
|
||||
{"ADDIS", 0x0400, 0xfe00, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false, false, true}, // $acD.hm += I
|
||||
{"CMPIS", 0x0600, 0xfe00, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false, false, true}, // FLAGS($acD - I)
|
||||
{"LRIS", 0x0800, 0xf800, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false, false, true}, // $(D+24) = I
|
||||
|
||||
{"ADDI", 0x0200, 0xfeff, Interpreter::addi, &DSPEmitter::addi, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $acD.hm += I
|
||||
{"XORI", 0x0220, 0xfeff, Interpreter::xori, &DSPEmitter::xori, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $acD.m ^= I
|
||||
{"ANDI", 0x0240, 0xfeff, Interpreter::andi, &DSPEmitter::andi, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $acD.m &= I
|
||||
{"ORI", 0x0260, 0xfeff, Interpreter::ori, &DSPEmitter::ori, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $acD.m |= I
|
||||
{"CMPI", 0x0280, 0xfeff, Interpreter::cmpi, &DSPEmitter::cmpi, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // FLAGS(($acD.hm - I) | $acD.l)
|
||||
{"ADDI", 0x0200, 0xfeff, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $acD.hm += I
|
||||
{"XORI", 0x0220, 0xfeff, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $acD.m ^= I
|
||||
{"ANDI", 0x0240, 0xfeff, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $acD.m &= I
|
||||
{"ORI", 0x0260, 0xfeff, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $acD.m |= I
|
||||
{"CMPI", 0x0280, 0xfeff, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // FLAGS(($acD.hm - I) | $acD.l)
|
||||
|
||||
{"ANDF", 0x02a0, 0xfeff, Interpreter::andf, &DSPEmitter::andf, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $sr.LZ = ($acD.m & I) == 0 ? 1 : 0
|
||||
{"ANDCF", 0x02c0, 0xfeff, Interpreter::andcf, &DSPEmitter::andcf, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $sr.LZ = ($acD.m & I) == I ? 1 : 0
|
||||
{"ANDF", 0x02a0, 0xfeff, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $sr.LZ = ($acD.m & I) == 0 ? 1 : 0
|
||||
{"ANDCF", 0x02c0, 0xfeff, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $sr.LZ = ($acD.m & I) == I ? 1 : 0
|
||||
|
||||
{"ILRR", 0x0210, 0xfefc, Interpreter::ilrr, &DSPEmitter::ilrr, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $acD.m = IMEM[$arS]
|
||||
{"ILRRD", 0x0214, 0xfefc, Interpreter::ilrrd, &DSPEmitter::ilrrd, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $acD.m = IMEM[$arS--]
|
||||
{"ILRRI", 0x0218, 0xfefc, Interpreter::ilrri, &DSPEmitter::ilrri, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $acD.m = IMEM[$arS++]
|
||||
{"ILRRN", 0x021c, 0xfefc, Interpreter::ilrrn, &DSPEmitter::ilrrn, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $acD.m = IMEM[$arS]; $arS += $ixS
|
||||
{"ILRR", 0x0210, 0xfefc, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $acD.m = IMEM[$arS]
|
||||
{"ILRRD", 0x0214, 0xfefc, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $acD.m = IMEM[$arS--]
|
||||
{"ILRRI", 0x0218, 0xfefc, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $acD.m = IMEM[$arS++]
|
||||
{"ILRRN", 0x021c, 0xfefc, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $acD.m = IMEM[$arS]; $arS += $ixS
|
||||
|
||||
// LOOPS
|
||||
{"LOOP", 0x0040, 0xffe0, Interpreter::loop, &DSPEmitter::loop, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, false, true, true, true, false}, // run next instruction $R times
|
||||
{"BLOOP", 0x0060, 0xffe0, Interpreter::bloop, &DSPEmitter::bloop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true, false}, // COMEFROM addr $R times
|
||||
{"LOOPI", 0x1000, 0xff00, Interpreter::loopi, &DSPEmitter::loopi, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}}, false, true, true, true, false}, // run next instruction I times
|
||||
{"BLOOPI", 0x1100, 0xff00, Interpreter::bloopi, &DSPEmitter::bloopi, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true, false}, // COMEFROM addr I times
|
||||
{"LOOP", 0x0040, 0xffe0, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, false, true, true, true, false}, // run next instruction $R times
|
||||
{"BLOOP", 0x0060, 0xffe0, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true, false}, // COMEFROM addr $R times
|
||||
{"LOOPI", 0x1000, 0xff00, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}}, false, true, true, true, false}, // run next instruction I times
|
||||
{"BLOOPI", 0x1100, 0xff00, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true, false}, // COMEFROM addr I times
|
||||
|
||||
// load and store value pointed by indexing reg and increment; LRR/SRR variants
|
||||
{"LRR", 0x1800, 0xff80, Interpreter::lrr, &DSPEmitter::lrr, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, // $D = MEM[$arS]
|
||||
{"LRRD", 0x1880, 0xff80, Interpreter::lrrd, &DSPEmitter::lrrd, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, // $D = MEM[$arS--]
|
||||
{"LRRI", 0x1900, 0xff80, Interpreter::lrri, &DSPEmitter::lrri, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, // $D = MEM[$arS++]
|
||||
{"LRRN", 0x1980, 0xff80, Interpreter::lrrn, &DSPEmitter::lrrn, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, // $D = MEM[$arS]; $arS += $ixS
|
||||
{"LRR", 0x1800, 0xff80, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, // $D = MEM[$arS]
|
||||
{"LRRD", 0x1880, 0xff80, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, // $D = MEM[$arS--]
|
||||
{"LRRI", 0x1900, 0xff80, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, // $D = MEM[$arS++]
|
||||
{"LRRN", 0x1980, 0xff80, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, // $D = MEM[$arS]; $arS += $ixS
|
||||
|
||||
{"SRR", 0x1a00, 0xff80, Interpreter::srr, &DSPEmitter::srr, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, // MEM[$arD] = $S
|
||||
{"SRRD", 0x1a80, 0xff80, Interpreter::srrd, &DSPEmitter::srrd, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, // MEM[$arD--] = $S
|
||||
{"SRRI", 0x1b00, 0xff80, Interpreter::srri, &DSPEmitter::srri, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, // MEM[$arD++] = $S
|
||||
{"SRRN", 0x1b80, 0xff80, Interpreter::srrn, &DSPEmitter::srrn, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, // MEM[$arD] = $S; $arD += $ixD
|
||||
{"SRR", 0x1a00, 0xff80, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, // MEM[$arD] = $S
|
||||
{"SRRD", 0x1a80, 0xff80, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, // MEM[$arD--] = $S
|
||||
{"SRRI", 0x1b00, 0xff80, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, // MEM[$arD++] = $S
|
||||
{"SRRN", 0x1b80, 0xff80, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, // MEM[$arD] = $S; $arD += $ixD
|
||||
|
||||
//2
|
||||
{"LRS", 0x2000, 0xf800, Interpreter::lrs, &DSPEmitter::lrs, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_MEM, 1, 0, 0, 0x00ff}}, false, false, false, false, false}, // $(D+24) = MEM[($cr[0-7] << 8) | I]
|
||||
{"SRS", 0x2800, 0xf800, Interpreter::srs, &DSPEmitter::srs, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG18, 1, 0, 8, 0x0700}}, false, false, false, false, false}, // MEM[($cr[0-7] << 8) | I] = $(S+24)
|
||||
{"LRS", 0x2000, 0xf800, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_MEM, 1, 0, 0, 0x00ff}}, false, false, false, false, false}, // $(D+24) = MEM[($cr[0-7] << 8) | I]
|
||||
{"SRS", 0x2800, 0xf800, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG18, 1, 0, 8, 0x0700}}, false, false, false, false, false}, // MEM[($cr[0-7] << 8) | I] = $(S+24)
|
||||
|
||||
// opcodes that can be extended
|
||||
|
||||
//3 - main opcode defined by 9 bits, extension defined by last 7 bits!!
|
||||
{"XORR", 0x3000, 0xfc80, Interpreter::xorr, &DSPEmitter::xorr, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD.m ^= $axS.h
|
||||
{"ANDR", 0x3400, 0xfc80, Interpreter::andr, &DSPEmitter::andr, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD.m &= $axS.h
|
||||
{"ORR", 0x3800, 0xfc80, Interpreter::orr, &DSPEmitter::orr, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD.m |= $axS.h
|
||||
{"ANDC", 0x3c00, 0xfe80, Interpreter::andc, &DSPEmitter::andc, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.m &= $ac(1-D).m
|
||||
{"ORC", 0x3e00, 0xfe80, Interpreter::orc, &DSPEmitter::orc, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.m |= $ac(1-D).m
|
||||
{"XORC", 0x3080, 0xfe80, Interpreter::xorc, &DSPEmitter::xorc, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.m ^= $ac(1-D).m
|
||||
{"NOT", 0x3280, 0xfe80, Interpreter::notc, &DSPEmitter::notc, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.m = ~$acD.m
|
||||
{"LSRNRX", 0x3480, 0xfc80, Interpreter::lsrnrx, &DSPEmitter::lsrnrx, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD >>=/<<= $axS.h[0-6]
|
||||
{"ASRNRX", 0x3880, 0xfc80, Interpreter::asrnrx, &DSPEmitter::asrnrx, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD >>=/<<= $axS.h[0-6] (arithmetic)
|
||||
{"LSRNR", 0x3c80, 0xfe80, Interpreter::lsrnr, &DSPEmitter::lsrnr, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD >>=/<<= $ac(1-D).m[0-6]
|
||||
{"ASRNR", 0x3e80, 0xfe80, Interpreter::asrnr, &DSPEmitter::asrnr, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD >>=/<<= $ac(1-D).m[0-6] (arithmetic)
|
||||
{"XORR", 0x3000, 0xfc80, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD.m ^= $axS.h
|
||||
{"ANDR", 0x3400, 0xfc80, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD.m &= $axS.h
|
||||
{"ORR", 0x3800, 0xfc80, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD.m |= $axS.h
|
||||
{"ANDC", 0x3c00, 0xfe80, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.m &= $ac(1-D).m
|
||||
{"ORC", 0x3e00, 0xfe80, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.m |= $ac(1-D).m
|
||||
{"XORC", 0x3080, 0xfe80, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.m ^= $ac(1-D).m
|
||||
{"NOT", 0x3280, 0xfe80, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.m = ~$acD.m
|
||||
{"LSRNRX", 0x3480, 0xfc80, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD >>=/<<= $axS.h[0-6]
|
||||
{"ASRNRX", 0x3880, 0xfc80, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD >>=/<<= $axS.h[0-6] (arithmetic)
|
||||
{"LSRNR", 0x3c80, 0xfe80, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD >>=/<<= $ac(1-D).m[0-6]
|
||||
{"ASRNR", 0x3e80, 0xfe80, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD >>=/<<= $ac(1-D).m[0-6] (arithmetic)
|
||||
|
||||
//4
|
||||
{"ADDR", 0x4000, 0xf800, Interpreter::addr, &DSPEmitter::addr, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false, false, true}, // $acD += $(S+24)
|
||||
{"ADDAX", 0x4800, 0xfc00, Interpreter::addax, &DSPEmitter::addax, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD += $axS
|
||||
{"ADD", 0x4c00, 0xfe00, Interpreter::add, &DSPEmitter::add, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD += $ac(1-D)
|
||||
{"ADDP", 0x4e00, 0xfe00, Interpreter::addp, &DSPEmitter::addp, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD += $prod
|
||||
{"ADDR", 0x4000, 0xf800, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false, false, true}, // $acD += $(S+24)
|
||||
{"ADDAX", 0x4800, 0xfc00, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD += $axS
|
||||
{"ADD", 0x4c00, 0xfe00, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD += $ac(1-D)
|
||||
{"ADDP", 0x4e00, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD += $prod
|
||||
|
||||
//5
|
||||
{"SUBR", 0x5000, 0xf800, Interpreter::subr, &DSPEmitter::subr, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false, false, true}, // $acD -= $(S+24)
|
||||
{"SUBAX", 0x5800, 0xfc00, Interpreter::subax, &DSPEmitter::subax, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD -= $axS
|
||||
{"SUB", 0x5c00, 0xfe00, Interpreter::sub, &DSPEmitter::sub, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD -= $ac(1-D)
|
||||
{"SUBP", 0x5e00, 0xfe00, Interpreter::subp, &DSPEmitter::subp, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD -= $prod
|
||||
{"SUBR", 0x5000, 0xf800, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false, false, true}, // $acD -= $(S+24)
|
||||
{"SUBAX", 0x5800, 0xfc00, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD -= $axS
|
||||
{"SUB", 0x5c00, 0xfe00, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD -= $ac(1-D)
|
||||
{"SUBP", 0x5e00, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD -= $prod
|
||||
|
||||
//6
|
||||
{"MOVR", 0x6000, 0xf800, Interpreter::movr, &DSPEmitter::movr, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false, false, true}, // $acD.hm = $(S+24); $acD.l = 0
|
||||
{"MOVAX", 0x6800, 0xfc00, Interpreter::movax, &DSPEmitter::movax, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD = $axS
|
||||
{"MOV", 0x6c00, 0xfe00, Interpreter::mov, &DSPEmitter::mov, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD = $ax(1-D)
|
||||
{"MOVP", 0x6e00, 0xfe00, Interpreter::movp, &DSPEmitter::movp, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD = $prod
|
||||
{"MOVR", 0x6000, 0xf800, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false, false, true}, // $acD.hm = $(S+24); $acD.l = 0
|
||||
{"MOVAX", 0x6800, 0xfc00, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD = $axS
|
||||
{"MOV", 0x6c00, 0xfe00, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD = $ax(1-D)
|
||||
{"MOVP", 0x6e00, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD = $prod
|
||||
|
||||
//7
|
||||
{"ADDAXL", 0x7000, 0xfc00, Interpreter::addaxl, &DSPEmitter::addaxl, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD += $axS.l
|
||||
{"INCM", 0x7400, 0xfe00, Interpreter::incm, &DSPEmitter::incm, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acsD++
|
||||
{"INC", 0x7600, 0xfe00, Interpreter::inc, &DSPEmitter::inc, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD++
|
||||
{"DECM", 0x7800, 0xfe00, Interpreter::decm, &DSPEmitter::decm, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acsD--
|
||||
{"DEC", 0x7a00, 0xfe00, Interpreter::dec, &DSPEmitter::dec, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD--
|
||||
{"NEG", 0x7c00, 0xfe00, Interpreter::neg, &DSPEmitter::neg, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD = -$acD
|
||||
{"MOVNP", 0x7e00, 0xfe00, Interpreter::movnp, &DSPEmitter::movnp, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD = -$prod
|
||||
{"ADDAXL", 0x7000, 0xfc00, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD += $axS.l
|
||||
{"INCM", 0x7400, 0xfe00, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acsD++
|
||||
{"INC", 0x7600, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD++
|
||||
{"DECM", 0x7800, 0xfe00, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acsD--
|
||||
{"DEC", 0x7a00, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD--
|
||||
{"NEG", 0x7c00, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD = -$acD
|
||||
{"MOVNP", 0x7e00, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD = -$prod
|
||||
|
||||
//8
|
||||
{"NX", 0x8000, 0xf700, Interpreter::nx, &DSPEmitter::nx, 1, 0, {}, true, false, false, false, false}, // extendable nop
|
||||
{"CLR", 0x8100, 0xf700, Interpreter::clr, &DSPEmitter::clr, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $acD = 0
|
||||
{"CMP", 0x8200, 0xff00, Interpreter::cmp, &DSPEmitter::cmp, 1, 0, {}, true, false, false, false, true}, // FLAGS($ac0 - $ac1)
|
||||
{"MULAXH", 0x8300, 0xff00, Interpreter::mulaxh, &DSPEmitter::mulaxh, 1, 0, {}, true, false, false, false, true}, // $prod = $ax0.h * $ax0.h
|
||||
{"CLRP", 0x8400, 0xff00, Interpreter::clrp, &DSPEmitter::clrp, 1, 0, {}, true, false, false, false, true}, // $prod = 0
|
||||
{"TSTPROD", 0x8500, 0xff00, Interpreter::tstprod, &DSPEmitter::tstprod,1, 0, {}, true, false, false, false, true}, // FLAGS($prod)
|
||||
{"TSTAXH", 0x8600, 0xfe00, Interpreter::tstaxh, &DSPEmitter::tstaxh, 1, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // FLAGS($axR.h)
|
||||
{"M2", 0x8a00, 0xff00, Interpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false, false}, // enable "$prod *= 2" after every multiplication
|
||||
{"M0", 0x8b00, 0xff00, Interpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false, false}, // disable "$prod *= 2" after every multiplication
|
||||
{"CLR15", 0x8c00, 0xff00, Interpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false, false}, // set normal multiplication
|
||||
{"SET15", 0x8d00, 0xff00, Interpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false, false}, // set unsigned multiplication in MUL
|
||||
{"SET16", 0x8e00, 0xff00, Interpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false, false}, // set 16 bit sign extension width
|
||||
{"SET40", 0x8f00, 0xff00, Interpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false, false, false}, // set 40 bit sign extension width
|
||||
{"NX", 0x8000, 0xf700, 1, 0, {}, true, false, false, false, false}, // extendable nop
|
||||
{"CLR", 0x8100, 0xf700, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $acD = 0
|
||||
{"CMP", 0x8200, 0xff00, 1, 0, {}, true, false, false, false, true}, // FLAGS($ac0 - $ac1)
|
||||
{"MULAXH", 0x8300, 0xff00, 1, 0, {}, true, false, false, false, true}, // $prod = $ax0.h * $ax0.h
|
||||
{"CLRP", 0x8400, 0xff00, 1, 0, {}, true, false, false, false, true}, // $prod = 0
|
||||
{"TSTPROD", 0x8500, 0xff00, 1, 0, {}, true, false, false, false, true}, // FLAGS($prod)
|
||||
{"TSTAXH", 0x8600, 0xfe00, 1, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // FLAGS($axR.h)
|
||||
{"M2", 0x8a00, 0xff00, 1, 0, {}, true, false, false, false, false}, // enable "$prod *= 2" after every multiplication
|
||||
{"M0", 0x8b00, 0xff00, 1, 0, {}, true, false, false, false, false}, // disable "$prod *= 2" after every multiplication
|
||||
{"CLR15", 0x8c00, 0xff00, 1, 0, {}, true, false, false, false, false}, // set normal multiplication
|
||||
{"SET15", 0x8d00, 0xff00, 1, 0, {}, true, false, false, false, false}, // set unsigned multiplication in MUL
|
||||
{"SET16", 0x8e00, 0xff00, 1, 0, {}, true, false, false, false, false}, // set 16 bit sign extension width
|
||||
{"SET40", 0x8f00, 0xff00, 1, 0, {}, true, false, false, false, false}, // set 40 bit sign extension width
|
||||
|
||||
//9
|
||||
{"MUL", 0x9000, 0xf700, Interpreter::mul, &DSPEmitter::mul, 1, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $prod = $axS.l * $axS.h
|
||||
{"ASR16", 0x9100, 0xf700, Interpreter::asr16, &DSPEmitter::asr16, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $acD >>= 16 (shifting in sign bits)
|
||||
{"MULMVZ", 0x9200, 0xf600, Interpreter::mulmvz, &DSPEmitter::mulmvz, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR.hm = $prod.hm; $acR.l = 0; $prod = $axS.l * $axS.h
|
||||
{"MULAC", 0x9400, 0xf600, Interpreter::mulac, &DSPEmitter::mulac, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR += $prod; $prod = $axS.l * $axS.h
|
||||
{"MULMV", 0x9600, 0xf600, Interpreter::mulmv, &DSPEmitter::mulmv, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR = $prod; $prod = $axS.l * $axS.h
|
||||
{"MUL", 0x9000, 0xf700, 1, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $prod = $axS.l * $axS.h
|
||||
{"ASR16", 0x9100, 0xf700, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $acD >>= 16 (shifting in sign bits)
|
||||
{"MULMVZ", 0x9200, 0xf600, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR.hm = $prod.hm; $acR.l = 0; $prod = $axS.l * $axS.h
|
||||
{"MULAC", 0x9400, 0xf600, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR += $prod; $prod = $axS.l * $axS.h
|
||||
{"MULMV", 0x9600, 0xf600, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR = $prod; $prod = $axS.l * $axS.h
|
||||
|
||||
//a-b
|
||||
{"MULX", 0xa000, 0xe700, Interpreter::mulx, &DSPEmitter::mulx, 1, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true, false, false, false, true}, // $prod = $ax0.S * $ax1.T
|
||||
{"ABS", 0xa100, 0xf700, Interpreter::abs, &DSPEmitter::abs, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $acD = abs($acD)
|
||||
{"MULXMVZ", 0xa200, 0xe600, Interpreter::mulxmvz, &DSPEmitter::mulxmvz,1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR.hm = $prod.hm; $acR.l = 0; $prod = $ax0.S * $ax1.T
|
||||
{"MULXAC", 0xa400, 0xe600, Interpreter::mulxac, &DSPEmitter::mulxac, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR += $prod; $prod = $ax0.S * $ax1.T
|
||||
{"MULXMV", 0xa600, 0xe600, Interpreter::mulxmv, &DSPEmitter::mulxmv, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR = $prod; $prod = $ax0.S * $ax1.T
|
||||
{"TST", 0xb100, 0xf700, Interpreter::tst, &DSPEmitter::tst, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // FLAGS($acR)
|
||||
{"MULX", 0xa000, 0xe700, 1, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true, false, false, false, true}, // $prod = $ax0.S * $ax1.T
|
||||
{"ABS", 0xa100, 0xf700, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $acD = abs($acD)
|
||||
{"MULXMVZ", 0xa200, 0xe600, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR.hm = $prod.hm; $acR.l = 0; $prod = $ax0.S * $ax1.T
|
||||
{"MULXAC", 0xa400, 0xe600, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR += $prod; $prod = $ax0.S * $ax1.T
|
||||
{"MULXMV", 0xa600, 0xe600, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR = $prod; $prod = $ax0.S * $ax1.T
|
||||
{"TST", 0xb100, 0xf700, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // FLAGS($acR)
|
||||
|
||||
//c-d
|
||||
{"MULC", 0xc000, 0xe700, Interpreter::mulc, &DSPEmitter::mulc, 1, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $prod = $acS.m * $axS.h
|
||||
{"CMPAR", 0xc100, 0xe700, Interpreter::cmpar, &DSPEmitter::cmpar, 1, 2, {{P_ACC, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 12, 0x1000}}, true, false, false, false, true}, // FLAGS($acS - axR.h)
|
||||
{"MULCMVZ", 0xc200, 0xe600, Interpreter::mulcmvz, &DSPEmitter::mulcmvz,1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR.hm, $acR.l, $prod = $prod.hm, 0, $acS.m * $axS.h
|
||||
{"MULCAC", 0xc400, 0xe600, Interpreter::mulcac, &DSPEmitter::mulcac, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR, $prod = $acR + $prod, $acS.m * $axS.h
|
||||
{"MULCMV", 0xc600, 0xe600, Interpreter::mulcmv, &DSPEmitter::mulcmv, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR, $prod = $prod, $acS.m * $axS.h
|
||||
{"MULC", 0xc000, 0xe700, 1, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $prod = $acS.m * $axS.h
|
||||
{"CMPAR", 0xc100, 0xe700, 1, 2, {{P_ACC, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 12, 0x1000}}, true, false, false, false, true}, // FLAGS($acS - axR.h)
|
||||
{"MULCMVZ", 0xc200, 0xe600, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR.hm, $acR.l, $prod = $prod.hm, 0, $acS.m * $axS.h
|
||||
{"MULCAC", 0xc400, 0xe600, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR, $prod = $acR + $prod, $acS.m * $axS.h
|
||||
{"MULCMV", 0xc600, 0xe600, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR, $prod = $prod, $acS.m * $axS.h
|
||||
|
||||
//e
|
||||
{"MADDX", 0xe000, 0xfc00, Interpreter::maddx, &DSPEmitter::maddx, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, // $prod += $ax0.S * $ax1.T
|
||||
{"MSUBX", 0xe400, 0xfc00, Interpreter::msubx, &DSPEmitter::msubx, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, // $prod -= $ax0.S * $ax1.T
|
||||
{"MADDC", 0xe800, 0xfc00, Interpreter::maddc, &DSPEmitter::maddc, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, // $prod += $acS.m * $axT.h
|
||||
{"MSUBC", 0xec00, 0xfc00, Interpreter::msubc, &DSPEmitter::msubc, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, // $prod -= $acS.m * $axT.h
|
||||
{"MADDX", 0xe000, 0xfc00, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, // $prod += $ax0.S * $ax1.T
|
||||
{"MSUBX", 0xe400, 0xfc00, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, // $prod -= $ax0.S * $ax1.T
|
||||
{"MADDC", 0xe800, 0xfc00, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, // $prod += $acS.m * $axT.h
|
||||
{"MSUBC", 0xec00, 0xfc00, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, // $prod -= $acS.m * $axT.h
|
||||
|
||||
//f
|
||||
{"LSL16", 0xf000, 0xfe00, Interpreter::lsl16, &DSPEmitter::lsl16, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR <<= 16
|
||||
{"MADD", 0xf200, 0xfe00, Interpreter::madd, &DSPEmitter::madd, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $prod += $axS.l * $axS.h
|
||||
{"LSR16", 0xf400, 0xfe00, Interpreter::lsr16, &DSPEmitter::lsr16, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR >>= 16
|
||||
{"MSUB", 0xf600, 0xfe00, Interpreter::msub, &DSPEmitter::msub, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $prod -= $axS.l * $axS.h
|
||||
{"ADDPAXZ", 0xf800, 0xfc00, Interpreter::addpaxz, &DSPEmitter::addpaxz,1, 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_AX, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.hm = $prod.hm + $ax.h; $acD.l = 0
|
||||
{"CLRL", 0xfc00, 0xfe00, Interpreter::clrl, &DSPEmitter::clrl, 1, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $acR.l = 0
|
||||
{"MOVPZ", 0xfe00, 0xfe00, Interpreter::movpz, &DSPEmitter::movpz, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.hm = $prod.hm; $acD.l = 0
|
||||
{"LSL16", 0xf000, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR <<= 16
|
||||
{"MADD", 0xf200, 0xfe00, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $prod += $axS.l * $axS.h
|
||||
{"LSR16", 0xf400, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR >>= 16
|
||||
{"MSUB", 0xf600, 0xfe00, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $prod -= $axS.l * $axS.h
|
||||
{"ADDPAXZ", 0xf800, 0xfc00, 1, 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_AX, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.hm = $prod.hm + $ax.h; $acD.l = 0
|
||||
{"CLRL", 0xfc00, 0xfe00, 1, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $acR.l = 0
|
||||
{"MOVPZ", 0xfe00, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.hm = $prod.hm; $acD.l = 0
|
||||
}};
|
||||
|
||||
const DSPOPCTemplate cw =
|
||||
{"CW", 0x0000, 0x0000, Interpreter::nop, nullptr, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}}, false, false, false, false, false};
|
||||
{"CW", 0x0000, 0x0000, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}}, false, false, false, false, false};
|
||||
|
||||
// extended opcodes
|
||||
|
||||
const std::array<DSPOPCTemplate, 25> s_opcodes_ext =
|
||||
{{
|
||||
{"XXX", 0x0000, 0x00fc, Interpreter::Ext::nop, &DSPEmitter::nop, 1, 1, {{P_VAL, 1, 0, 0, 0x00ff}}, false, false, false, false, false}, // no operation
|
||||
{"XXX", 0x0000, 0x00fc, 1, 1, {{P_VAL, 1, 0, 0, 0x00ff}}, false, false, false, false, false}, // no operation
|
||||
|
||||
{"DR", 0x0004, 0x00fc, Interpreter::Ext::dr, &DSPEmitter::dr, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arR--
|
||||
{"IR", 0x0008, 0x00fc, Interpreter::Ext::ir, &DSPEmitter::ir, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arR++
|
||||
{"NR", 0x000c, 0x00fc, Interpreter::Ext::nr, &DSPEmitter::nr, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arR += $ixR
|
||||
{"MV", 0x0010, 0x00f0, Interpreter::Ext::mv, &DSPEmitter::mv, 1, 2, {{P_REG18, 1, 0, 2, 0x000c}, {P_REG1C, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $(D+24) = $(S+28)
|
||||
{"DR", 0x0004, 0x00fc, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arR--
|
||||
{"IR", 0x0008, 0x00fc, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arR++
|
||||
{"NR", 0x000c, 0x00fc, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arR += $ixR
|
||||
{"MV", 0x0010, 0x00f0, 1, 2, {{P_REG18, 1, 0, 2, 0x000c}, {P_REG1C, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $(D+24) = $(S+28)
|
||||
|
||||
{"S", 0x0020, 0x00e4, Interpreter::Ext::s, &DSPEmitter::s, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false, false, false, false, false}, // MEM[$D++] = $(S+28)
|
||||
{"SN", 0x0024, 0x00e4, Interpreter::Ext::sn, &DSPEmitter::sn, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false, false, false, false, false}, // MEM[$D] = $(D+28); $D += $(D+4)
|
||||
{"S", 0x0020, 0x00e4, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false, false, false, false, false}, // MEM[$D++] = $(S+28)
|
||||
{"SN", 0x0024, 0x00e4, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false, false, false, false, false}, // MEM[$D] = $(D+28); $D += $(D+4)
|
||||
|
||||
{"L", 0x0040, 0x00c4, Interpreter::Ext::l, &DSPEmitter::l, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $(D+24) = MEM[$S++]
|
||||
{"LN", 0x0044, 0x00c4, Interpreter::Ext::ln, &DSPEmitter::ln, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $(D+24) = MEM[$S]; $S += $(S+4)
|
||||
{"L", 0x0040, 0x00c4, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $(D+24) = MEM[$S++]
|
||||
{"LN", 0x0044, 0x00c4, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $(D+24) = MEM[$S]; $S += $(S+4)
|
||||
|
||||
{"LS", 0x0080, 0x00ce, Interpreter::Ext::ls, &DSPEmitter::ls, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false, false, false, false}, // $(D+24) = MEM[$ar0++]; MEM[$ar3++] = $acS.m
|
||||
{"SL", 0x0082, 0x00ce, Interpreter::Ext::sl, &DSPEmitter::sl, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false, false, false, false}, // MEM[$ar0++] = $acS.m; $(D+24) = MEM[$ar3++]
|
||||
{"LSN", 0x0084, 0x00ce, Interpreter::Ext::lsn, &DSPEmitter::lsn, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false, false, false, false}, // $(D+24) = MEM[$ar0]; MEM[$ar3++] = $acS.m; $ar0 += $ix0
|
||||
{"SLN", 0x0086, 0x00ce, Interpreter::Ext::sln, &DSPEmitter::sln, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false, false, false, false}, // MEM[$ar0] = $acS.m; $(D+24) = MEM[$ar3++]; $ar0 += $ix0
|
||||
{"LSM", 0x0088, 0x00ce, Interpreter::Ext::lsm, &DSPEmitter::lsm, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false, false, false, false}, // $(D+24) = MEM[$ar0++]; MEM[$ar3] = $acS.m; $ar3 += $ix3
|
||||
{"SLM", 0x008a, 0x00ce, Interpreter::Ext::slm, &DSPEmitter::slm, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false, false, false, false}, // MEM[$ar0++] = $acS.m; $(D+24) = MEM[$ar3]; $ar3 += $ix3
|
||||
{"LSNM", 0x008c, 0x00ce, Interpreter::Ext::lsnm, &DSPEmitter::lsnm, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false, false, false, false}, // $(D+24) = MEM[$ar0]; MEM[$ar3] = $acS.m; $ar0 += $ix0; $ar3 += $ix3
|
||||
{"SLNM", 0x008e, 0x00ce, Interpreter::Ext::slnm, &DSPEmitter::slnm, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false, false, false, false}, // MEM[$ar0] = $acS.m; $(D+24) = MEM[$ar3]; $ar0 += $ix0; $ar3 += $ix3
|
||||
{"LS", 0x0080, 0x00ce, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false, false, false, false}, // $(D+24) = MEM[$ar0++]; MEM[$ar3++] = $acS.m
|
||||
{"SL", 0x0082, 0x00ce, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false, false, false, false}, // MEM[$ar0++] = $acS.m; $(D+24) = MEM[$ar3++]
|
||||
{"LSN", 0x0084, 0x00ce, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false, false, false, false}, // $(D+24) = MEM[$ar0]; MEM[$ar3++] = $acS.m; $ar0 += $ix0
|
||||
{"SLN", 0x0086, 0x00ce, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false, false, false, false}, // MEM[$ar0] = $acS.m; $(D+24) = MEM[$ar3++]; $ar0 += $ix0
|
||||
{"LSM", 0x0088, 0x00ce, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false, false, false, false}, // $(D+24) = MEM[$ar0++]; MEM[$ar3] = $acS.m; $ar3 += $ix3
|
||||
{"SLM", 0x008a, 0x00ce, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false, false, false, false}, // MEM[$ar0++] = $acS.m; $(D+24) = MEM[$ar3]; $ar3 += $ix3
|
||||
{"LSNM", 0x008c, 0x00ce, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false, false, false, false}, // $(D+24) = MEM[$ar0]; MEM[$ar3] = $acS.m; $ar0 += $ix0; $ar3 += $ix3
|
||||
{"SLNM", 0x008e, 0x00ce, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false, false, false, false}, // MEM[$ar0] = $acS.m; $(D+24) = MEM[$ar3]; $ar0 += $ix0; $ar3 += $ix3
|
||||
|
||||
{"LDAX", 0x00c3, 0x00cf, Interpreter::Ext::ldax, &DSPEmitter::ldax, 1, 2, {{P_AX, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, false, false, false, false, false}, // $axR.h = MEM[$arS++]; $axR.l = MEM[$ar3++]
|
||||
{"LDAXN", 0x00c7, 0x00cf, Interpreter::Ext::ldaxn, &DSPEmitter::ldaxn, 1, 2, {{P_AX, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, false, false, false, false, false}, // $axR.h = MEM[$arS]; $axR.l = MEM[$ar3++]; $arS += $ixS
|
||||
{"LDAXM", 0x00cb, 0x00cf, Interpreter::Ext::ldaxm, &DSPEmitter::ldaxm, 1, 2, {{P_AX, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, false, false, false, false, false}, // $axR.h = MEM[$arS++]; $axR.l = MEM[$ar3]; $ar3 += $ix3
|
||||
{"LDAXNM", 0x00cf, 0x00cf, Interpreter::Ext::ldaxnm, &DSPEmitter::ldaxnm, 1, 2, {{P_AX, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, false, false, false, false, false}, // $axR.h = MEM[$arS]; $axR.l = MEM[$ar3]; $arS += $ixS; $ar3 += $ix3
|
||||
{"LDAX", 0x00c3, 0x00cf, 1, 2, {{P_AX, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, false, false, false, false, false}, // $axR.h = MEM[$arS++]; $axR.l = MEM[$ar3++]
|
||||
{"LDAXN", 0x00c7, 0x00cf, 1, 2, {{P_AX, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, false, false, false, false, false}, // $axR.h = MEM[$arS]; $axR.l = MEM[$ar3++]; $arS += $ixS
|
||||
{"LDAXM", 0x00cb, 0x00cf, 1, 2, {{P_AX, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, false, false, false, false, false}, // $axR.h = MEM[$arS++]; $axR.l = MEM[$ar3]; $ar3 += $ix3
|
||||
{"LDAXNM", 0x00cf, 0x00cf, 1, 2, {{P_AX, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, false, false, false, false, false}, // $axR.h = MEM[$arS]; $axR.l = MEM[$ar3]; $arS += $ixS; $ar3 += $ix3
|
||||
|
||||
{"LD", 0x00c0, 0x00cc, Interpreter::Ext::ld, &DSPEmitter::ld, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $ax0.D = MEM[$arS++]; $ax1.R = MEM[$ar3++]
|
||||
{"LDN", 0x00c4, 0x00cc, Interpreter::Ext::ldn, &DSPEmitter::ldn, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $ax0.D = MEM[$arS]; $ax1.R = MEM[$ar3++]; $arS += $ixS
|
||||
{"LDM", 0x00c8, 0x00cc, Interpreter::Ext::ldm, &DSPEmitter::ldm, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $ax0.D = MEM[$arS++]; $ax1.R = MEM[$ar3]; $ar3 += $ix3
|
||||
{"LDNM", 0x00cc, 0x00cc, Interpreter::Ext::ldnm, &DSPEmitter::ldnm, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $ax0.D = MEM[$arS]; $ax1.R = MEM[$ar3]; $arS += $ixS; $ar3 += $ix3
|
||||
{"LD", 0x00c0, 0x00cc, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $ax0.D = MEM[$arS++]; $ax1.R = MEM[$ar3++]
|
||||
{"LDN", 0x00c4, 0x00cc, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $ax0.D = MEM[$arS]; $ax1.R = MEM[$ar3++]; $arS += $ixS
|
||||
{"LDM", 0x00c8, 0x00cc, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $ax0.D = MEM[$arS++]; $ax1.R = MEM[$ar3]; $ar3 += $ix3
|
||||
{"LDNM", 0x00cc, 0x00cc, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $ax0.D = MEM[$arS]; $ax1.R = MEM[$ar3]; $arS += $ixS; $ar3 += $ix3
|
||||
}};
|
||||
|
||||
const std::array<pdlabel_t, 96> pdlabels =
|
||||
|
@ -625,5 +621,8 @@ void InitInstructionTable()
|
|||
}
|
||||
|
||||
writeBackLogIdx.fill(-1);
|
||||
|
||||
// Ensure the interpreter tables are all set up, as JITs also rely on them.
|
||||
Interpreter::InitInstructionTables();
|
||||
}
|
||||
} // namespace DSP
|
||||
|
|
|
@ -11,7 +11,6 @@
|
|||
#include <string>
|
||||
|
||||
#include "Core/DSP/DSPCommon.h"
|
||||
#include "Core/DSP/Jit/x64/DSPEmitter.h"
|
||||
|
||||
namespace DSP
|
||||
{
|
||||
|
@ -68,16 +67,10 @@ struct param2_t
|
|||
|
||||
struct DSPOPCTemplate
|
||||
{
|
||||
using InterpreterFunction = void (*)(UDSPInstruction);
|
||||
using JITFunction = void (JIT::x64::DSPEmitter::*)(UDSPInstruction);
|
||||
|
||||
const char* name;
|
||||
u16 opcode;
|
||||
u16 opcode_mask;
|
||||
|
||||
InterpreterFunction intFunc;
|
||||
JITFunction jitFunc;
|
||||
|
||||
u8 size;
|
||||
u8 param_count;
|
||||
param2_t params[8];
|
||||
|
|
|
@ -0,0 +1,389 @@
|
|||
// Copyright 2018 Dolphin Emulator Project
|
||||
// Licensed under GPLv2+
|
||||
// Refer to the license.txt file included.
|
||||
|
||||
#include "Core/DSP/Interpreter/DSPIntTables.h"
|
||||
|
||||
#include <algorithm>
|
||||
#include <array>
|
||||
|
||||
#include "Common/CommonTypes.h"
|
||||
#include "Core/DSP/Interpreter/DSPIntExtOps.h"
|
||||
#include "Core/DSP/Interpreter/DSPInterpreter.h"
|
||||
|
||||
namespace DSP::Interpreter
|
||||
{
|
||||
struct InterpreterOpInfo
|
||||
{
|
||||
u16 opcode;
|
||||
u16 mask;
|
||||
InterpreterFunction function;
|
||||
};
|
||||
|
||||
// clang-format off
|
||||
constexpr std::array<InterpreterOpInfo, 214> s_opcodes
|
||||
{{
|
||||
{0x0000, 0xfffc, nop},
|
||||
|
||||
{0x0004, 0xfffc, dar},
|
||||
{0x0008, 0xfffc, iar},
|
||||
{0x000c, 0xfffc, subarn},
|
||||
{0x0010, 0xfff0, addarn},
|
||||
|
||||
{0x0021, 0xffff, halt},
|
||||
|
||||
{0x02d0, 0xffff, ret},
|
||||
{0x02d1, 0xffff, ret},
|
||||
{0x02d2, 0xffff, ret},
|
||||
{0x02d3, 0xffff, ret},
|
||||
{0x02d4, 0xffff, ret},
|
||||
{0x02d5, 0xffff, ret},
|
||||
{0x02d6, 0xffff, ret},
|
||||
{0x02d7, 0xffff, ret},
|
||||
{0x02d8, 0xffff, ret},
|
||||
{0x02d9, 0xffff, ret},
|
||||
{0x02da, 0xffff, ret},
|
||||
{0x02db, 0xffff, ret},
|
||||
{0x02dc, 0xffff, ret},
|
||||
{0x02dd, 0xffff, ret},
|
||||
{0x02de, 0xffff, ret},
|
||||
{0x02df, 0xffff, ret},
|
||||
|
||||
{0x02ff, 0xffff, rti},
|
||||
|
||||
{0x02b0, 0xffff, call},
|
||||
{0x02b1, 0xffff, call},
|
||||
{0x02b2, 0xffff, call},
|
||||
{0x02b3, 0xffff, call},
|
||||
{0x02b4, 0xffff, call},
|
||||
{0x02b5, 0xffff, call},
|
||||
{0x02b6, 0xffff, call},
|
||||
{0x02b7, 0xffff, call},
|
||||
{0x02b8, 0xffff, call},
|
||||
{0x02b9, 0xffff, call},
|
||||
{0x02ba, 0xffff, call},
|
||||
{0x02bb, 0xffff, call},
|
||||
{0x02bc, 0xffff, call},
|
||||
{0x02bd, 0xffff, call},
|
||||
{0x02be, 0xffff, call},
|
||||
{0x02bf, 0xffff, call},
|
||||
|
||||
{0x0270, 0xffff, ifcc},
|
||||
{0x0271, 0xffff, ifcc},
|
||||
{0x0272, 0xffff, ifcc},
|
||||
{0x0273, 0xffff, ifcc},
|
||||
{0x0274, 0xffff, ifcc},
|
||||
{0x0275, 0xffff, ifcc},
|
||||
{0x0276, 0xffff, ifcc},
|
||||
{0x0277, 0xffff, ifcc},
|
||||
{0x0278, 0xffff, ifcc},
|
||||
{0x0279, 0xffff, ifcc},
|
||||
{0x027a, 0xffff, ifcc},
|
||||
{0x027b, 0xffff, ifcc},
|
||||
{0x027c, 0xffff, ifcc},
|
||||
{0x027d, 0xffff, ifcc},
|
||||
{0x027e, 0xffff, ifcc},
|
||||
{0x027f, 0xffff, ifcc},
|
||||
|
||||
{0x0290, 0xffff, jcc},
|
||||
{0x0291, 0xffff, jcc},
|
||||
{0x0292, 0xffff, jcc},
|
||||
{0x0293, 0xffff, jcc},
|
||||
{0x0294, 0xffff, jcc},
|
||||
{0x0295, 0xffff, jcc},
|
||||
{0x0296, 0xffff, jcc},
|
||||
{0x0297, 0xffff, jcc},
|
||||
{0x0298, 0xffff, jcc},
|
||||
{0x0299, 0xffff, jcc},
|
||||
{0x029a, 0xffff, jcc},
|
||||
{0x029b, 0xffff, jcc},
|
||||
{0x029c, 0xffff, jcc},
|
||||
{0x029d, 0xffff, jcc},
|
||||
{0x029e, 0xffff, jcc},
|
||||
{0x029f, 0xffff, jcc},
|
||||
|
||||
{0x1700, 0xff1f, jmprcc},
|
||||
{0x1701, 0xff1f, jmprcc},
|
||||
{0x1702, 0xff1f, jmprcc},
|
||||
{0x1703, 0xff1f, jmprcc},
|
||||
{0x1704, 0xff1f, jmprcc},
|
||||
{0x1705, 0xff1f, jmprcc},
|
||||
{0x1706, 0xff1f, jmprcc},
|
||||
{0x1707, 0xff1f, jmprcc},
|
||||
{0x1708, 0xff1f, jmprcc},
|
||||
{0x1709, 0xff1f, jmprcc},
|
||||
{0x170a, 0xff1f, jmprcc},
|
||||
{0x170b, 0xff1f, jmprcc},
|
||||
{0x170c, 0xff1f, jmprcc},
|
||||
{0x170d, 0xff1f, jmprcc},
|
||||
{0x170e, 0xff1f, jmprcc},
|
||||
{0x170f, 0xff1f, jmprcc},
|
||||
|
||||
{0x1710, 0xff1f, callr},
|
||||
{0x1711, 0xff1f, callr},
|
||||
{0x1712, 0xff1f, callr},
|
||||
{0x1713, 0xff1f, callr},
|
||||
{0x1714, 0xff1f, callr},
|
||||
{0x1715, 0xff1f, callr},
|
||||
{0x1716, 0xff1f, callr},
|
||||
{0x1717, 0xff1f, callr},
|
||||
{0x1718, 0xff1f, callr},
|
||||
{0x1719, 0xff1f, callr},
|
||||
{0x171a, 0xff1f, callr},
|
||||
{0x171b, 0xff1f, callr},
|
||||
{0x171c, 0xff1f, callr},
|
||||
{0x171d, 0xff1f, callr},
|
||||
{0x171e, 0xff1f, callr},
|
||||
{0x171f, 0xff1f, callr},
|
||||
|
||||
{0x1200, 0xff00, sbclr},
|
||||
{0x1300, 0xff00, sbset},
|
||||
|
||||
{0x1400, 0xfec0, lsl},
|
||||
{0x1440, 0xfec0, lsr},
|
||||
{0x1480, 0xfec0, asl},
|
||||
{0x14c0, 0xfec0, asr},
|
||||
|
||||
// these two were discovered by ector
|
||||
{0x02ca, 0xffff, lsrn},
|
||||
{0x02cb, 0xffff, asrn},
|
||||
|
||||
{0x0080, 0xffe0, lri},
|
||||
{0x00c0, 0xffe0, lr},
|
||||
{0x00e0, 0xffe0, sr},
|
||||
|
||||
{0x1c00, 0xfc00, mrr},
|
||||
|
||||
{0x1600, 0xff00, si},
|
||||
|
||||
{0x0400, 0xfe00, addis},
|
||||
{0x0600, 0xfe00, cmpis},
|
||||
{0x0800, 0xf800, lris},
|
||||
|
||||
{0x0200, 0xfeff, addi},
|
||||
{0x0220, 0xfeff, xori},
|
||||
{0x0240, 0xfeff, andi},
|
||||
{0x0260, 0xfeff, ori},
|
||||
{0x0280, 0xfeff, cmpi},
|
||||
|
||||
{0x02a0, 0xfeff, andf},
|
||||
{0x02c0, 0xfeff, andcf},
|
||||
|
||||
{0x0210, 0xfefc, ilrr},
|
||||
{0x0214, 0xfefc, ilrrd},
|
||||
{0x0218, 0xfefc, ilrri},
|
||||
{0x021c, 0xfefc, ilrrn},
|
||||
|
||||
// LOOPS
|
||||
{0x0040, 0xffe0, loop},
|
||||
{0x0060, 0xffe0, bloop},
|
||||
{0x1000, 0xff00, loopi},
|
||||
{0x1100, 0xff00, bloopi},
|
||||
|
||||
// load and store value pointed by indexing reg and increment; LRR/SRR variants
|
||||
{0x1800, 0xff80, lrr},
|
||||
{0x1880, 0xff80, lrrd},
|
||||
{0x1900, 0xff80, lrri},
|
||||
{0x1980, 0xff80, lrrn},
|
||||
|
||||
{0x1a00, 0xff80, srr},
|
||||
{0x1a80, 0xff80, srrd},
|
||||
{0x1b00, 0xff80, srri},
|
||||
{0x1b80, 0xff80, srrn},
|
||||
|
||||
// 2
|
||||
{0x2000, 0xf800, lrs},
|
||||
{0x2800, 0xf800, srs},
|
||||
|
||||
// opcodes that can be extended
|
||||
|
||||
// 3 - main opcode defined by 9 bits, extension defined by last 7 bits!!
|
||||
{0x3000, 0xfc80, xorr},
|
||||
{0x3400, 0xfc80, andr},
|
||||
{0x3800, 0xfc80, orr},
|
||||
{0x3c00, 0xfe80, andc},
|
||||
{0x3e00, 0xfe80, orc},
|
||||
{0x3080, 0xfe80, xorc},
|
||||
{0x3280, 0xfe80, notc},
|
||||
{0x3480, 0xfc80, lsrnrx},
|
||||
{0x3880, 0xfc80, asrnrx},
|
||||
{0x3c80, 0xfe80, lsrnr},
|
||||
{0x3e80, 0xfe80, asrnr},
|
||||
|
||||
// 4
|
||||
{0x4000, 0xf800, addr},
|
||||
{0x4800, 0xfc00, addax},
|
||||
{0x4c00, 0xfe00, add},
|
||||
{0x4e00, 0xfe00, addp},
|
||||
|
||||
// 5
|
||||
{0x5000, 0xf800, subr},
|
||||
{0x5800, 0xfc00, subax},
|
||||
{0x5c00, 0xfe00, sub},
|
||||
{0x5e00, 0xfe00, subp},
|
||||
|
||||
// 6
|
||||
{0x6000, 0xf800, movr},
|
||||
{0x6800, 0xfc00, movax},
|
||||
{0x6c00, 0xfe00, mov},
|
||||
{0x6e00, 0xfe00, movp},
|
||||
|
||||
// 7
|
||||
{0x7000, 0xfc00, addaxl},
|
||||
{0x7400, 0xfe00, incm},
|
||||
{0x7600, 0xfe00, inc},
|
||||
{0x7800, 0xfe00, decm},
|
||||
{0x7a00, 0xfe00, dec},
|
||||
{0x7c00, 0xfe00, neg},
|
||||
{0x7e00, 0xfe00, movnp},
|
||||
|
||||
// 8
|
||||
{0x8000, 0xf700, nx},
|
||||
{0x8100, 0xf700, clr},
|
||||
{0x8200, 0xff00, cmp},
|
||||
{0x8300, 0xff00, mulaxh},
|
||||
{0x8400, 0xff00, clrp},
|
||||
{0x8500, 0xff00, tstprod},
|
||||
{0x8600, 0xfe00, tstaxh},
|
||||
{0x8a00, 0xff00, srbith},
|
||||
{0x8b00, 0xff00, srbith},
|
||||
{0x8c00, 0xff00, srbith},
|
||||
{0x8d00, 0xff00, srbith},
|
||||
{0x8e00, 0xff00, srbith},
|
||||
{0x8f00, 0xff00, srbith},
|
||||
|
||||
// 9
|
||||
{0x9000, 0xf700, mul},
|
||||
{0x9100, 0xf700, asr16},
|
||||
{0x9200, 0xf600, mulmvz},
|
||||
{0x9400, 0xf600, mulac},
|
||||
{0x9600, 0xf600, mulmv},
|
||||
|
||||
// A-B
|
||||
{0xa000, 0xe700, mulx},
|
||||
{0xa100, 0xf700, abs},
|
||||
{0xa200, 0xe600, mulxmvz},
|
||||
{0xa400, 0xe600, mulxac},
|
||||
{0xa600, 0xe600, mulxmv},
|
||||
{0xb100, 0xf700, tst},
|
||||
|
||||
// C-D
|
||||
{0xc000, 0xe700, mulc},
|
||||
{0xc100, 0xe700, cmpar},
|
||||
{0xc200, 0xe600, mulcmvz},
|
||||
{0xc400, 0xe600, mulcac},
|
||||
{0xc600, 0xe600, mulcmv},
|
||||
|
||||
// E
|
||||
{0xe000, 0xfc00, maddx},
|
||||
{0xe400, 0xfc00, msubx},
|
||||
{0xe800, 0xfc00, maddc},
|
||||
{0xec00, 0xfc00, msubc},
|
||||
|
||||
// F
|
||||
{0xf000, 0xfe00, lsl16},
|
||||
{0xf200, 0xfe00, madd},
|
||||
{0xf400, 0xfe00, lsr16},
|
||||
{0xf600, 0xfe00, msub},
|
||||
{0xf800, 0xfc00, addpaxz},
|
||||
{0xfc00, 0xfe00, clrl},
|
||||
{0xfe00, 0xfe00, movpz},
|
||||
}};
|
||||
|
||||
constexpr std::array<InterpreterOpInfo, 25> s_opcodes_ext
|
||||
{{
|
||||
{0x0000, 0x00fc, Ext::nop},
|
||||
|
||||
{0x0004, 0x00fc, Ext::dr},
|
||||
{0x0008, 0x00fc, Ext::ir},
|
||||
{0x000c, 0x00fc, Ext::nr},
|
||||
{0x0010, 0x00f0, Ext::mv},
|
||||
|
||||
{0x0020, 0x00e4, Ext::s},
|
||||
{0x0024, 0x00e4, Ext::sn},
|
||||
|
||||
{0x0040, 0x00c4, Ext::l},
|
||||
{0x0044, 0x00c4, Ext::ln},
|
||||
|
||||
{0x0080, 0x00ce, Ext::ls},
|
||||
{0x0082, 0x00ce, Ext::sl},
|
||||
{0x0084, 0x00ce, Ext::lsn},
|
||||
{0x0086, 0x00ce, Ext::sln},
|
||||
{0x0088, 0x00ce, Ext::lsm},
|
||||
{0x008a, 0x00ce, Ext::slm},
|
||||
{0x008c, 0x00ce, Ext::lsnm},
|
||||
{0x008e, 0x00ce, Ext::slnm},
|
||||
|
||||
{0x00c3, 0x00cf, Ext::ldax},
|
||||
{0x00c7, 0x00cf, Ext::ldaxn},
|
||||
{0x00cb, 0x00cf, Ext::ldaxm},
|
||||
{0x00cf, 0x00cf, Ext::ldaxnm},
|
||||
|
||||
{0x00c0, 0x00cc, Ext::ld},
|
||||
{0x00c4, 0x00cc, Ext::ldn},
|
||||
{0x00c8, 0x00cc, Ext::ldm},
|
||||
{0x00cc, 0x00cc, Ext::ldnm},
|
||||
}};
|
||||
// clang-format on
|
||||
|
||||
namespace
|
||||
{
|
||||
std::array<InterpreterFunction, 65536> s_op_table;
|
||||
std::array<InterpreterFunction, 256> s_ext_op_table;
|
||||
bool s_tables_initialized = false;
|
||||
|
||||
template <size_t N>
|
||||
auto FindByOpcode(UDSPInstruction opcode, const std::array<InterpreterOpInfo, N>& data)
|
||||
{
|
||||
return std::find_if(data.cbegin(), data.cend(),
|
||||
[opcode](const auto& info) { return (opcode & info.mask) == info.opcode; });
|
||||
}
|
||||
} // Anonymous namespace
|
||||
|
||||
InterpreterFunction GetOp(UDSPInstruction inst)
|
||||
{
|
||||
return s_op_table[inst];
|
||||
}
|
||||
|
||||
InterpreterFunction GetExtOp(UDSPInstruction inst)
|
||||
{
|
||||
const bool has_seven_bit_extension = (inst >> 12) == 0x3;
|
||||
|
||||
if (has_seven_bit_extension)
|
||||
return s_ext_op_table[inst & 0x7F];
|
||||
|
||||
return s_ext_op_table[inst & 0xFF];
|
||||
}
|
||||
|
||||
void InitInstructionTables()
|
||||
{
|
||||
if (s_tables_initialized)
|
||||
return;
|
||||
|
||||
// ext op table
|
||||
for (size_t i = 0; i < s_ext_op_table.size(); i++)
|
||||
{
|
||||
s_ext_op_table[i] = nop;
|
||||
|
||||
const auto iter = FindByOpcode(static_cast<UDSPInstruction>(i), s_opcodes_ext);
|
||||
if (iter == s_opcodes_ext.cend())
|
||||
continue;
|
||||
|
||||
s_ext_op_table[i] = iter->function;
|
||||
}
|
||||
|
||||
// op table
|
||||
for (size_t i = 0; i < s_op_table.size(); i++)
|
||||
{
|
||||
s_op_table[i] = nop;
|
||||
|
||||
const auto iter = FindByOpcode(static_cast<UDSPInstruction>(i), s_opcodes);
|
||||
if (iter == s_opcodes.cend())
|
||||
continue;
|
||||
|
||||
s_op_table[i] = iter->function;
|
||||
}
|
||||
|
||||
s_tables_initialized = true;
|
||||
}
|
||||
} // namespace DSP::Interpreter
|
|
@ -0,0 +1,16 @@
|
|||
// Copyright 2018 Dolphin Emulator Project
|
||||
// Licensed under GPLv2+
|
||||
// Refer to the license.txt file included.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "Core/DSP/DSPCommon.h"
|
||||
|
||||
namespace DSP::Interpreter
|
||||
{
|
||||
using InterpreterFunction = void (*)(UDSPInstruction);
|
||||
|
||||
InterpreterFunction GetOp(UDSPInstruction inst);
|
||||
InterpreterFunction GetExtOp(UDSPInstruction inst);
|
||||
void InitInstructionTables();
|
||||
} // namespace DSP::Interpreter
|
|
@ -12,6 +12,7 @@
|
|||
#include "Core/DSP/DSPCore.h"
|
||||
#include "Core/DSP/DSPMemoryMap.h"
|
||||
#include "Core/DSP/DSPTables.h"
|
||||
#include "Core/DSP/Interpreter/DSPIntTables.h"
|
||||
|
||||
namespace DSP
|
||||
{
|
||||
|
@ -25,10 +26,10 @@ void ExecuteInstruction(const UDSPInstruction inst)
|
|||
|
||||
if (opcode_template->extended)
|
||||
{
|
||||
GetExtOpTemplate(inst)->intFunc(inst);
|
||||
GetExtOp(inst)(inst);
|
||||
}
|
||||
|
||||
opcode_template->intFunc(inst);
|
||||
GetOp(inst)(inst);
|
||||
|
||||
if (opcode_template->extended)
|
||||
{
|
||||
|
|
|
@ -19,6 +19,8 @@
|
|||
#include "Core/DSP/DSPHost.h"
|
||||
#include "Core/DSP/DSPMemoryMap.h"
|
||||
#include "Core/DSP/DSPTables.h"
|
||||
#include "Core/DSP/Interpreter/DSPIntTables.h"
|
||||
#include "Core/DSP/Jit/x64/DSPJitTables.h"
|
||||
|
||||
using namespace Gen;
|
||||
|
||||
|
@ -32,6 +34,7 @@ DSPEmitter::DSPEmitter()
|
|||
: m_compile_status_register{SR_INT_ENABLE | SR_EXT_INT_ENABLE}, m_blocks(MAX_BLOCKS),
|
||||
m_block_size(MAX_BLOCKS), m_block_links(MAX_BLOCKS)
|
||||
{
|
||||
x64::InitInstructionTables();
|
||||
AllocCodeSpace(COMPILED_CODE_SIZE);
|
||||
|
||||
CompileDispatcher();
|
||||
|
@ -139,9 +142,11 @@ void DSPEmitter::FallBackToInterpreter(UDSPInstruction inst)
|
|||
}
|
||||
|
||||
// Fall back to interpreter
|
||||
const auto interpreter_function = Interpreter::GetOp(inst);
|
||||
|
||||
m_gpr.PushRegs();
|
||||
ASSERT_MSG(DSPLLE, op_template->intFunc, "No function for %04x", inst);
|
||||
ABI_CallFunctionC16(op_template->intFunc, inst);
|
||||
ASSERT_MSG(DSPLLE, interpreter_function != nullptr, "No function for %04x", inst);
|
||||
ABI_CallFunctionC16(interpreter_function, inst);
|
||||
m_gpr.PopRegs();
|
||||
}
|
||||
|
||||
|
@ -153,33 +158,36 @@ void DSPEmitter::EmitInstruction(UDSPInstruction inst)
|
|||
// Call extended
|
||||
if (op_template->extended)
|
||||
{
|
||||
const DSPOPCTemplate* const ext_op_template = GetExtOpTemplate(inst);
|
||||
const auto jit_function = GetExtOp(inst);
|
||||
|
||||
if (!ext_op_template->jitFunc)
|
||||
if (jit_function)
|
||||
{
|
||||
(this->*jit_function)(inst);
|
||||
ext_is_jit = true;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Fall back to interpreter
|
||||
const auto interpreter_function = Interpreter::GetExtOp(inst);
|
||||
|
||||
m_gpr.PushRegs();
|
||||
ABI_CallFunctionC16(ext_op_template->intFunc, inst);
|
||||
ABI_CallFunctionC16(interpreter_function, inst);
|
||||
m_gpr.PopRegs();
|
||||
INFO_LOG(DSPLLE, "Instruction not JITed(ext part): %04x", inst);
|
||||
ext_is_jit = false;
|
||||
}
|
||||
else
|
||||
{
|
||||
(this->*ext_op_template->jitFunc)(inst);
|
||||
ext_is_jit = true;
|
||||
}
|
||||
}
|
||||
|
||||
// Main instruction
|
||||
if (!op_template->jitFunc)
|
||||
const auto jit_function = GetOp(inst);
|
||||
if (jit_function)
|
||||
{
|
||||
FallBackToInterpreter(inst);
|
||||
INFO_LOG(DSPLLE, "Instruction not JITed(main part): %04x", inst);
|
||||
(this->*jit_function)(inst);
|
||||
}
|
||||
else
|
||||
{
|
||||
(this->*op_template->jitFunc)(inst);
|
||||
FallBackToInterpreter(inst);
|
||||
INFO_LOG(DSPLLE, "Instruction not JITed(main part): %04x", inst);
|
||||
}
|
||||
|
||||
// Backlog
|
||||
|
@ -281,7 +289,9 @@ void DSPEmitter::Compile(u16 start_addr)
|
|||
{
|
||||
break;
|
||||
}
|
||||
else if (!opcode->jitFunc)
|
||||
|
||||
const auto jit_function = GetOp(inst);
|
||||
if (!jit_function)
|
||||
{
|
||||
// look at g_dsp.pc if we actually branched
|
||||
MOV(16, R(AX), M_SDSP_pc());
|
||||
|
|
|
@ -0,0 +1,388 @@
|
|||
// Copyright 2018 Dolphin Emulator Project
|
||||
// Licensed under GPLv2+
|
||||
// Refer to the license.txt file included.
|
||||
|
||||
#include "Core/DSP/Jit/x64/DSPJitTables.h"
|
||||
|
||||
#include <algorithm>
|
||||
#include <array>
|
||||
|
||||
#include "Common/CommonTypes.h"
|
||||
#include "Core/DSP/Jit/x64/DSPEmitter.h"
|
||||
|
||||
namespace DSP::JIT::x64
|
||||
{
|
||||
struct JITOpInfo
|
||||
{
|
||||
u16 opcode;
|
||||
u16 mask;
|
||||
JITFunction function;
|
||||
};
|
||||
|
||||
// clang-format off
|
||||
const std::array<JITOpInfo, 214> s_opcodes =
|
||||
{{
|
||||
{0x0000, 0xfffc, &DSPEmitter::nop},
|
||||
|
||||
{0x0004, 0xfffc, &DSPEmitter::dar},
|
||||
{0x0008, 0xfffc, &DSPEmitter::iar},
|
||||
{0x000c, 0xfffc, &DSPEmitter::subarn},
|
||||
{0x0010, 0xfff0, &DSPEmitter::addarn},
|
||||
|
||||
{0x0021, 0xffff, &DSPEmitter::halt},
|
||||
|
||||
{0x02d0, 0xffff, &DSPEmitter::ret},
|
||||
{0x02d1, 0xffff, &DSPEmitter::ret},
|
||||
{0x02d2, 0xffff, &DSPEmitter::ret},
|
||||
{0x02d3, 0xffff, &DSPEmitter::ret},
|
||||
{0x02d4, 0xffff, &DSPEmitter::ret},
|
||||
{0x02d5, 0xffff, &DSPEmitter::ret},
|
||||
{0x02d6, 0xffff, &DSPEmitter::ret},
|
||||
{0x02d7, 0xffff, &DSPEmitter::ret},
|
||||
{0x02d8, 0xffff, &DSPEmitter::ret},
|
||||
{0x02d9, 0xffff, &DSPEmitter::ret},
|
||||
{0x02da, 0xffff, &DSPEmitter::ret},
|
||||
{0x02db, 0xffff, &DSPEmitter::ret},
|
||||
{0x02dc, 0xffff, &DSPEmitter::ret},
|
||||
{0x02dd, 0xffff, &DSPEmitter::ret},
|
||||
{0x02de, 0xffff, &DSPEmitter::ret},
|
||||
{0x02df, 0xffff, &DSPEmitter::ret},
|
||||
|
||||
{0x02ff, 0xffff, &DSPEmitter::rti},
|
||||
|
||||
{0x02b0, 0xffff, &DSPEmitter::call},
|
||||
{0x02b1, 0xffff, &DSPEmitter::call},
|
||||
{0x02b2, 0xffff, &DSPEmitter::call},
|
||||
{0x02b3, 0xffff, &DSPEmitter::call},
|
||||
{0x02b4, 0xffff, &DSPEmitter::call},
|
||||
{0x02b5, 0xffff, &DSPEmitter::call},
|
||||
{0x02b6, 0xffff, &DSPEmitter::call},
|
||||
{0x02b7, 0xffff, &DSPEmitter::call},
|
||||
{0x02b8, 0xffff, &DSPEmitter::call},
|
||||
{0x02b9, 0xffff, &DSPEmitter::call},
|
||||
{0x02ba, 0xffff, &DSPEmitter::call},
|
||||
{0x02bb, 0xffff, &DSPEmitter::call},
|
||||
{0x02bc, 0xffff, &DSPEmitter::call},
|
||||
{0x02bd, 0xffff, &DSPEmitter::call},
|
||||
{0x02be, 0xffff, &DSPEmitter::call},
|
||||
{0x02bf, 0xffff, &DSPEmitter::call},
|
||||
|
||||
{0x0270, 0xffff, &DSPEmitter::ifcc},
|
||||
{0x0271, 0xffff, &DSPEmitter::ifcc},
|
||||
{0x0272, 0xffff, &DSPEmitter::ifcc},
|
||||
{0x0273, 0xffff, &DSPEmitter::ifcc},
|
||||
{0x0274, 0xffff, &DSPEmitter::ifcc},
|
||||
{0x0275, 0xffff, &DSPEmitter::ifcc},
|
||||
{0x0276, 0xffff, &DSPEmitter::ifcc},
|
||||
{0x0277, 0xffff, &DSPEmitter::ifcc},
|
||||
{0x0278, 0xffff, &DSPEmitter::ifcc},
|
||||
{0x0279, 0xffff, &DSPEmitter::ifcc},
|
||||
{0x027a, 0xffff, &DSPEmitter::ifcc},
|
||||
{0x027b, 0xffff, &DSPEmitter::ifcc},
|
||||
{0x027c, 0xffff, &DSPEmitter::ifcc},
|
||||
{0x027d, 0xffff, &DSPEmitter::ifcc},
|
||||
{0x027e, 0xffff, &DSPEmitter::ifcc},
|
||||
{0x027f, 0xffff, &DSPEmitter::ifcc},
|
||||
|
||||
{0x0290, 0xffff, &DSPEmitter::jcc},
|
||||
{0x0291, 0xffff, &DSPEmitter::jcc},
|
||||
{0x0292, 0xffff, &DSPEmitter::jcc},
|
||||
{0x0293, 0xffff, &DSPEmitter::jcc},
|
||||
{0x0294, 0xffff, &DSPEmitter::jcc},
|
||||
{0x0295, 0xffff, &DSPEmitter::jcc},
|
||||
{0x0296, 0xffff, &DSPEmitter::jcc},
|
||||
{0x0297, 0xffff, &DSPEmitter::jcc},
|
||||
{0x0298, 0xffff, &DSPEmitter::jcc},
|
||||
{0x0299, 0xffff, &DSPEmitter::jcc},
|
||||
{0x029a, 0xffff, &DSPEmitter::jcc},
|
||||
{0x029b, 0xffff, &DSPEmitter::jcc},
|
||||
{0x029c, 0xffff, &DSPEmitter::jcc},
|
||||
{0x029d, 0xffff, &DSPEmitter::jcc},
|
||||
{0x029e, 0xffff, &DSPEmitter::jcc},
|
||||
{0x029f, 0xffff, &DSPEmitter::jcc},
|
||||
|
||||
{0x1700, 0xff1f, &DSPEmitter::jmprcc},
|
||||
{0x1701, 0xff1f, &DSPEmitter::jmprcc},
|
||||
{0x1702, 0xff1f, &DSPEmitter::jmprcc},
|
||||
{0x1703, 0xff1f, &DSPEmitter::jmprcc},
|
||||
{0x1704, 0xff1f, &DSPEmitter::jmprcc},
|
||||
{0x1705, 0xff1f, &DSPEmitter::jmprcc},
|
||||
{0x1706, 0xff1f, &DSPEmitter::jmprcc},
|
||||
{0x1707, 0xff1f, &DSPEmitter::jmprcc},
|
||||
{0x1708, 0xff1f, &DSPEmitter::jmprcc},
|
||||
{0x1709, 0xff1f, &DSPEmitter::jmprcc},
|
||||
{0x170a, 0xff1f, &DSPEmitter::jmprcc},
|
||||
{0x170b, 0xff1f, &DSPEmitter::jmprcc},
|
||||
{0x170c, 0xff1f, &DSPEmitter::jmprcc},
|
||||
{0x170d, 0xff1f, &DSPEmitter::jmprcc},
|
||||
{0x170e, 0xff1f, &DSPEmitter::jmprcc},
|
||||
{0x170f, 0xff1f, &DSPEmitter::jmprcc},
|
||||
|
||||
{0x1710, 0xff1f, &DSPEmitter::callr},
|
||||
{0x1711, 0xff1f, &DSPEmitter::callr},
|
||||
{0x1712, 0xff1f, &DSPEmitter::callr},
|
||||
{0x1713, 0xff1f, &DSPEmitter::callr},
|
||||
{0x1714, 0xff1f, &DSPEmitter::callr},
|
||||
{0x1715, 0xff1f, &DSPEmitter::callr},
|
||||
{0x1716, 0xff1f, &DSPEmitter::callr},
|
||||
{0x1717, 0xff1f, &DSPEmitter::callr},
|
||||
{0x1718, 0xff1f, &DSPEmitter::callr},
|
||||
{0x1719, 0xff1f, &DSPEmitter::callr},
|
||||
{0x171a, 0xff1f, &DSPEmitter::callr},
|
||||
{0x171b, 0xff1f, &DSPEmitter::callr},
|
||||
{0x171c, 0xff1f, &DSPEmitter::callr},
|
||||
{0x171d, 0xff1f, &DSPEmitter::callr},
|
||||
{0x171e, 0xff1f, &DSPEmitter::callr},
|
||||
{0x171f, 0xff1f, &DSPEmitter::callr},
|
||||
|
||||
{0x1200, 0xff00, &DSPEmitter::sbclr},
|
||||
{0x1300, 0xff00, &DSPEmitter::sbset},
|
||||
|
||||
{0x1400, 0xfec0, &DSPEmitter::lsl},
|
||||
{0x1440, 0xfec0, &DSPEmitter::lsr},
|
||||
{0x1480, 0xfec0, &DSPEmitter::asl},
|
||||
{0x14c0, 0xfec0, &DSPEmitter::asr},
|
||||
|
||||
// These two were discovered by ector
|
||||
{0x02ca, 0xffff, &DSPEmitter::lsrn},
|
||||
{0x02cb, 0xffff, &DSPEmitter::asrn},
|
||||
|
||||
{0x0080, 0xffe0, &DSPEmitter::lri},
|
||||
{0x00c0, 0xffe0, &DSPEmitter::lr},
|
||||
{0x00e0, 0xffe0, &DSPEmitter::sr},
|
||||
|
||||
{0x1c00, 0xfc00, &DSPEmitter::mrr},
|
||||
|
||||
{0x1600, 0xff00, &DSPEmitter::si},
|
||||
|
||||
{0x0400, 0xfe00, &DSPEmitter::addis},
|
||||
{0x0600, 0xfe00, &DSPEmitter::cmpis},
|
||||
{0x0800, 0xf800, &DSPEmitter::lris},
|
||||
|
||||
{0x0200, 0xfeff, &DSPEmitter::addi},
|
||||
{0x0220, 0xfeff, &DSPEmitter::xori},
|
||||
{0x0240, 0xfeff, &DSPEmitter::andi},
|
||||
{0x0260, 0xfeff, &DSPEmitter::ori},
|
||||
{0x0280, 0xfeff, &DSPEmitter::cmpi},
|
||||
|
||||
{0x02a0, 0xfeff, &DSPEmitter::andf},
|
||||
{0x02c0, 0xfeff, &DSPEmitter::andcf},
|
||||
|
||||
{0x0210, 0xfefc, &DSPEmitter::ilrr},
|
||||
{0x0214, 0xfefc, &DSPEmitter::ilrrd},
|
||||
{0x0218, 0xfefc, &DSPEmitter::ilrri},
|
||||
{0x021c, 0xfefc, &DSPEmitter::ilrrn},
|
||||
|
||||
// LOOPS
|
||||
{0x0040, 0xffe0, &DSPEmitter::loop},
|
||||
{0x0060, 0xffe0, &DSPEmitter::bloop},
|
||||
{0x1000, 0xff00, &DSPEmitter::loopi},
|
||||
{0x1100, 0xff00, &DSPEmitter::bloopi},
|
||||
|
||||
// Load and store value pointed by indexing reg and increment; LRR/SRR variants
|
||||
{0x1800, 0xff80, &DSPEmitter::lrr},
|
||||
{0x1880, 0xff80, &DSPEmitter::lrrd},
|
||||
{0x1900, 0xff80, &DSPEmitter::lrri},
|
||||
{0x1980, 0xff80, &DSPEmitter::lrrn},
|
||||
|
||||
{0x1a00, 0xff80, &DSPEmitter::srr},
|
||||
{0x1a80, 0xff80, &DSPEmitter::srrd},
|
||||
{0x1b00, 0xff80, &DSPEmitter::srri},
|
||||
{0x1b80, 0xff80, &DSPEmitter::srrn},
|
||||
|
||||
// 2
|
||||
{0x2000, 0xf800, &DSPEmitter::lrs},
|
||||
{0x2800, 0xf800, &DSPEmitter::srs},
|
||||
|
||||
// opcodes that can be extended
|
||||
|
||||
// 3 - main opcode defined by 9 bits, extension defined by last 7 bits!!
|
||||
{0x3000, 0xfc80, &DSPEmitter::xorr},
|
||||
{0x3400, 0xfc80, &DSPEmitter::andr},
|
||||
{0x3800, 0xfc80, &DSPEmitter::orr},
|
||||
{0x3c00, 0xfe80, &DSPEmitter::andc},
|
||||
{0x3e00, 0xfe80, &DSPEmitter::orc},
|
||||
{0x3080, 0xfe80, &DSPEmitter::xorc},
|
||||
{0x3280, 0xfe80, &DSPEmitter::notc},
|
||||
{0x3480, 0xfc80, &DSPEmitter::lsrnrx},
|
||||
{0x3880, 0xfc80, &DSPEmitter::asrnrx},
|
||||
{0x3c80, 0xfe80, &DSPEmitter::lsrnr},
|
||||
{0x3e80, 0xfe80, &DSPEmitter::asrnr},
|
||||
|
||||
// 4
|
||||
{0x4000, 0xf800, &DSPEmitter::addr},
|
||||
{0x4800, 0xfc00, &DSPEmitter::addax},
|
||||
{0x4c00, 0xfe00, &DSPEmitter::add},
|
||||
{0x4e00, 0xfe00, &DSPEmitter::addp},
|
||||
|
||||
// 5
|
||||
{0x5000, 0xf800, &DSPEmitter::subr},
|
||||
{0x5800, 0xfc00, &DSPEmitter::subax},
|
||||
{0x5c00, 0xfe00, &DSPEmitter::sub},
|
||||
{0x5e00, 0xfe00, &DSPEmitter::subp},
|
||||
|
||||
// 6
|
||||
{0x6000, 0xf800, &DSPEmitter::movr},
|
||||
{0x6800, 0xfc00, &DSPEmitter::movax},
|
||||
{0x6c00, 0xfe00, &DSPEmitter::mov},
|
||||
{0x6e00, 0xfe00, &DSPEmitter::movp},
|
||||
|
||||
// 7
|
||||
{0x7000, 0xfc00, &DSPEmitter::addaxl},
|
||||
{0x7400, 0xfe00, &DSPEmitter::incm},
|
||||
{0x7600, 0xfe00, &DSPEmitter::inc},
|
||||
{0x7800, 0xfe00, &DSPEmitter::decm},
|
||||
{0x7a00, 0xfe00, &DSPEmitter::dec},
|
||||
{0x7c00, 0xfe00, &DSPEmitter::neg},
|
||||
{0x7e00, 0xfe00, &DSPEmitter::movnp},
|
||||
|
||||
// 8
|
||||
{0x8000, 0xf700, &DSPEmitter::nx},
|
||||
{0x8100, 0xf700, &DSPEmitter::clr},
|
||||
{0x8200, 0xff00, &DSPEmitter::cmp},
|
||||
{0x8300, 0xff00, &DSPEmitter::mulaxh},
|
||||
{0x8400, 0xff00, &DSPEmitter::clrp},
|
||||
{0x8500, 0xff00, &DSPEmitter::tstprod},
|
||||
{0x8600, 0xfe00, &DSPEmitter::tstaxh},
|
||||
{0x8a00, 0xff00, &DSPEmitter::srbith},
|
||||
{0x8b00, 0xff00, &DSPEmitter::srbith},
|
||||
{0x8c00, 0xff00, &DSPEmitter::srbith},
|
||||
{0x8d00, 0xff00, &DSPEmitter::srbith},
|
||||
{0x8e00, 0xff00, &DSPEmitter::srbith},
|
||||
{0x8f00, 0xff00, &DSPEmitter::srbith},
|
||||
|
||||
// 9
|
||||
{0x9000, 0xf700, &DSPEmitter::mul},
|
||||
{0x9100, 0xf700, &DSPEmitter::asr16},
|
||||
{0x9200, 0xf600, &DSPEmitter::mulmvz},
|
||||
{0x9400, 0xf600, &DSPEmitter::mulac},
|
||||
{0x9600, 0xf600, &DSPEmitter::mulmv},
|
||||
|
||||
// A-B
|
||||
{0xa000, 0xe700, &DSPEmitter::mulx},
|
||||
{0xa100, 0xf700, &DSPEmitter::abs},
|
||||
{0xa200, 0xe600, &DSPEmitter::mulxmvz},
|
||||
{0xa400, 0xe600, &DSPEmitter::mulxac},
|
||||
{0xa600, 0xe600, &DSPEmitter::mulxmv},
|
||||
{0xb100, 0xf700, &DSPEmitter::tst},
|
||||
|
||||
// C-D
|
||||
{0xc000, 0xe700, &DSPEmitter::mulc},
|
||||
{0xc100, 0xe700, &DSPEmitter::cmpar},
|
||||
{0xc200, 0xe600, &DSPEmitter::mulcmvz},
|
||||
{0xc400, 0xe600, &DSPEmitter::mulcac},
|
||||
{0xc600, 0xe600, &DSPEmitter::mulcmv},
|
||||
|
||||
// E
|
||||
{0xe000, 0xfc00, &DSPEmitter::maddx},
|
||||
{0xe400, 0xfc00, &DSPEmitter::msubx},
|
||||
{0xe800, 0xfc00, &DSPEmitter::maddc},
|
||||
{0xec00, 0xfc00, &DSPEmitter::msubc},
|
||||
|
||||
// F
|
||||
{0xf000, 0xfe00, &DSPEmitter::lsl16},
|
||||
{0xf200, 0xfe00, &DSPEmitter::madd},
|
||||
{0xf400, 0xfe00, &DSPEmitter::lsr16},
|
||||
{0xf600, 0xfe00, &DSPEmitter::msub},
|
||||
{0xf800, 0xfc00, &DSPEmitter::addpaxz},
|
||||
{0xfc00, 0xfe00, &DSPEmitter::clrl},
|
||||
{0xfe00, 0xfe00, &DSPEmitter::movpz},
|
||||
}};
|
||||
|
||||
constexpr std::array<JITOpInfo, 25> s_opcodes_ext
|
||||
{{
|
||||
{0x0000, 0x00fc, &DSPEmitter::nop},
|
||||
|
||||
{0x0004, 0x00fc, &DSPEmitter::dr},
|
||||
{0x0008, 0x00fc, &DSPEmitter::ir},
|
||||
{0x000c, 0x00fc, &DSPEmitter::nr},
|
||||
{0x0010, 0x00f0, &DSPEmitter::mv},
|
||||
|
||||
{0x0020, 0x00e4, &DSPEmitter::s},
|
||||
{0x0024, 0x00e4, &DSPEmitter::sn},
|
||||
|
||||
{0x0040, 0x00c4, &DSPEmitter::l},
|
||||
{0x0044, 0x00c4, &DSPEmitter::ln},
|
||||
|
||||
{0x0080, 0x00ce, &DSPEmitter::ls},
|
||||
{0x0082, 0x00ce, &DSPEmitter::sl},
|
||||
{0x0084, 0x00ce, &DSPEmitter::lsn},
|
||||
{0x0086, 0x00ce, &DSPEmitter::sln},
|
||||
{0x0088, 0x00ce, &DSPEmitter::lsm},
|
||||
{0x008a, 0x00ce, &DSPEmitter::slm},
|
||||
{0x008c, 0x00ce, &DSPEmitter::lsnm},
|
||||
{0x008e, 0x00ce, &DSPEmitter::slnm},
|
||||
|
||||
{0x00c3, 0x00cf, &DSPEmitter::ldax},
|
||||
{0x00c7, 0x00cf, &DSPEmitter::ldaxn},
|
||||
{0x00cb, 0x00cf, &DSPEmitter::ldaxm},
|
||||
{0x00cf, 0x00cf, &DSPEmitter::ldaxnm},
|
||||
|
||||
{0x00c0, 0x00cc, &DSPEmitter::ld},
|
||||
{0x00c4, 0x00cc, &DSPEmitter::ldn},
|
||||
{0x00c8, 0x00cc, &DSPEmitter::ldm},
|
||||
{0x00cc, 0x00cc, &DSPEmitter::ldnm},
|
||||
}};
|
||||
// clang-format on
|
||||
|
||||
namespace
|
||||
{
|
||||
std::array<JITFunction, 65536> s_op_table;
|
||||
std::array<JITFunction, 256> s_ext_op_table;
|
||||
bool s_tables_initialized = false;
|
||||
|
||||
template <size_t N>
|
||||
auto FindByOpcode(UDSPInstruction opcode, const std::array<JITOpInfo, N>& data)
|
||||
{
|
||||
return std::find_if(data.cbegin(), data.cend(),
|
||||
[opcode](const auto& info) { return (opcode & info.mask) == info.opcode; });
|
||||
}
|
||||
} // Anonymous namespace
|
||||
|
||||
JITFunction GetOp(UDSPInstruction inst)
|
||||
{
|
||||
return s_op_table[inst];
|
||||
}
|
||||
|
||||
JITFunction GetExtOp(UDSPInstruction inst)
|
||||
{
|
||||
const bool has_seven_bit_extension = (inst >> 12) == 0x3;
|
||||
|
||||
if (has_seven_bit_extension)
|
||||
return s_ext_op_table[inst & 0x7F];
|
||||
|
||||
return s_ext_op_table[inst & 0xFF];
|
||||
}
|
||||
|
||||
void InitInstructionTables()
|
||||
{
|
||||
if (s_tables_initialized)
|
||||
return;
|
||||
|
||||
// ext op table
|
||||
for (size_t i = 0; i < s_ext_op_table.size(); i++)
|
||||
{
|
||||
s_ext_op_table[i] = nullptr;
|
||||
|
||||
const auto iter = FindByOpcode(static_cast<UDSPInstruction>(i), s_opcodes_ext);
|
||||
if (iter == s_opcodes_ext.cend())
|
||||
continue;
|
||||
|
||||
s_ext_op_table[i] = iter->function;
|
||||
}
|
||||
|
||||
// op table
|
||||
for (size_t i = 0; i < s_op_table.size(); i++)
|
||||
{
|
||||
s_op_table[i] = nullptr;
|
||||
|
||||
const auto iter = FindByOpcode(static_cast<UDSPInstruction>(i), s_opcodes);
|
||||
if (iter == s_opcodes.cend())
|
||||
continue;
|
||||
|
||||
s_op_table[i] = iter->function;
|
||||
}
|
||||
|
||||
s_tables_initialized = true;
|
||||
}
|
||||
} // namespace DSP::JIT::x64
|
|
@ -0,0 +1,18 @@
|
|||
// Copyright 2018 Dolphin Emulator Project
|
||||
// Licensed under GPLv2+
|
||||
// Refer to the license.txt file included.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "Core/DSP/DSPCommon.h"
|
||||
|
||||
namespace DSP::JIT::x64
|
||||
{
|
||||
class DSPEmitter;
|
||||
|
||||
using JITFunction = void (DSPEmitter::*)(UDSPInstruction);
|
||||
|
||||
JITFunction GetOp(UDSPInstruction inst);
|
||||
JITFunction GetExtOp(UDSPInstruction inst);
|
||||
void InitInstructionTables();
|
||||
} // namespace DSP::JIT::x64
|
|
@ -25,6 +25,7 @@
|
|||
#include "Core/DSP/DSPHost.h"
|
||||
#include "Core/DSP/DSPTables.h"
|
||||
#include "Core/DSP/Interpreter/DSPInterpreter.h"
|
||||
#include "Core/DSP/Jit/x64/DSPEmitter.h"
|
||||
#include "Core/HW/DSPLLE/DSPLLEGlobals.h"
|
||||
#include "Core/HW/Memmap.h"
|
||||
#include "Core/Host.h"
|
||||
|
|
Loading…
Reference in New Issue