DSPSpy: Split main dsp_base logic from interrupt handlers
This is so that interrupt handlers can be manually specified in tests that need them.
This commit is contained in:
Pokechu22
parent
87dc668522
commit
5f7c852d22
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@ -1,9 +1,3 @@
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; This is the trojan program we send to the DSP from DSPSpy to figure it out.
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REGS_BASE: equ 0x0f80
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MEM_HI: equ 0x0f7E
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MEM_LO: equ 0x0f7F
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; Interrupt vectors 8 vectors, 2 opcodes each
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jmp irq0
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jmp irq1
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@ -14,279 +8,5 @@ MEM_LO: equ 0x0f7F
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jmp irq6
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jmp irq7
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; Main code (and normal entrypoint) at 0x10
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sbset #0x02
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sbset #0x03
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sbclr #0x04
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sbset #0x05
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sbset #0x06
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s16
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lri $CR, #0x00ff
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clr $acc1
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clr $acc0
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; get address of memory dump and copy it to DRAM
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call 0x807e
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si @DMBH, #0x8888
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si @DMBL, #0xdead
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si @DIRQ, #0x0001
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call 0x8078
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andi $ac0.m, #0x7fff
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lrs $ac1.m, @CMBL
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sr @MEM_HI, $ac0.m
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sr @MEM_LO, $ac1.m
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lri $ax0.l, #0
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lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
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lri $ax0.h, #0x2000
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lr $ac0.l, @MEM_HI
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lr $ac0.m, @MEM_LO
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call do_dma
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; get address of registers and DMA them to ram
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call 0x807e
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si @DMBH, #0x8888
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si @DMBL, #0xbeef
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si @DIRQ, #0x0001
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call 0x8078
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andi $ac0.m, #0x7fff
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lrs $ac1.m, @CMBL
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sr @MEM_HI, $ac0.m
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sr @MEM_LO, $ac1.m
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lri $ax0.l, #REGS_BASE
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lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
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lri $ax0.h, #0x80
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lr $ac0.l, @MEM_HI
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lr $ac0.m, @MEM_LO
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call do_dma
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; Read in all the registers from RAM
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lri $ar0, #REGS_BASE+1
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lrri $ar1, @$ar0
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lrri $ar2, @$ar0
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lrri $ar3, @$ar0
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lrri $ix0, @$ar0
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lrri $ix1, @$ar0
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lrri $ix2, @$ar0
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lrri $ix3, @$ar0
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lrri $wr0, @$ar0
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lrri $wr1, @$ar0
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lrri $wr2, @$ar0
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lrri $wr3, @$ar0
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lrri $st0, @$ar0
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lrri $st1, @$ar0
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lrri $st2, @$ar0
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lrri $st3, @$ar0
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lrri $ac0.h, @$ar0
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lrri $ac1.h, @$ar0
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lrri $cr, @$ar0
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lrri $sr, @$ar0
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lrri $prod.l, @$ar0
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lrri $prod.m1, @$ar0
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lrri $prod.h, @$ar0
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lrri $prod.m2, @$ar0
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lrri $ax0.l, @$ar0
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lrri $ax1.l, @$ar0
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lrri $ax0.h, @$ar0
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lrri $ax1.h, @$ar0
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lrri $ac0.l, @$ar0
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lrri $ac1.l, @$ar0
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lrri $ac0.m, @$ar0
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lrri $ac1.m, @$ar0
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lr $ar0, @REGS_BASE
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jmp start_of_test
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; This is where we jump when we're done testing, see above.
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; We just fall into a loop, playing dead until someone resets the DSP.
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end_of_test:
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nop
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jmp end_of_test
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; Utility function to do DMA.
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do_dma:
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sr @DSMAH, $ac0.l
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sr @DSMAL, $ac0.m
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sr @DSPA, $ax0.l
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sr @DSCR, $ax1.l
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sr @DSBL, $ax0.h ; This kicks off the DMA.
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wait_dma_finish:
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lr $ac1.m, @DSCR
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andcf $ac1.m, #0x4
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jlz wait_dma_finish
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ret
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; IRQ handlers. Just send back exception# and die
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irq0:
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lri $ac0.m, #0x0000
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jmp irq
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irq1:
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lri $ac0.m, #0x0001
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jmp irq
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irq2:
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lri $ac0.m, #0x0002
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jmp irq
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irq3:
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lri $ac0.m, #0x0003
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jmp irq
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irq4:
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lri $ac0.m, #0x0004
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jmp irq
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irq5:
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lrs $ac0.m, @DMBH
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andcf $ac0.m, #0x8000
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jlz irq5
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si @DMBH, #0x8005
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si @DMBL, #0x0000
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si @DIRQ, #0x0001
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lri $ac0.m, #0xbbbb
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sr @0xffda, $ac0.m ; pred scale
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sr @0xffdb, $ac0.m ; yn1
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lr $ix2, @ARAM
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sr @0xffdc, $ac0.m ; yn2
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rti
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irq6:
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lri $ac0.m, #0x0006
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jmp irq
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irq7:
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lri $ac0.m, #0x0007
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irq:
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lrs $ac1.m, @DMBH
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andcf $ac1.m, #0x8000
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jlz irq
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si @DMBH, #0x8bad
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;sr @DMBL, $wr3 ; ???
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sr @DMBL, $ac0.m ; Exception number
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si @DIRQ, #0x0001
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halt ; Through some magic this allows us to properly ack the exception in dspspy
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;rti ; allow dumping of ucodes which cause exceptions...probably not safe at all
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; DMA:s the current state of the registers back to the PowerPC. To do this,
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; it must write the contents of all regs to DRAM.
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send_back:
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; first, store $sr so we can modify it
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sr @(REGS_BASE + 19), $sr
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set16
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; Now store $wr0, as it must be 0xffff for srri to work as we expect
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sr @(REGS_BASE + 8), $wr0
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lri $wr0, #0xffff
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; store registers to reg table
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sr @REGS_BASE, $ar0
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lri $ar0, #(REGS_BASE + 1)
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srri @$ar0, $ar1
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srri @$ar0, $ar2
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srri @$ar0, $ar3
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srri @$ar0, $ix0
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srri @$ar0, $ix1
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srri @$ar0, $ix2
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srri @$ar0, $ix3
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; skip $wr0 since we already stored and modified it
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iar $ar0
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srri @$ar0, $wr1
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srri @$ar0, $wr2
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srri @$ar0, $wr3
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srri @$ar0, $st0
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srri @$ar0, $st1
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srri @$ar0, $st2
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srri @$ar0, $st3
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srri @$ar0, $ac0.h
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srri @$ar0, $ac1.h
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srri @$ar0, $cr
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; skip $sr since we already stored and modified it
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iar $ar0
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srri @$ar0, $prod.l
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srri @$ar0, $prod.m1
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srri @$ar0, $prod.h
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srri @$ar0, $prod.m2
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srri @$ar0, $ax0.l
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srri @$ar0, $ax1.l
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srri @$ar0, $ax0.h
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srri @$ar0, $ax1.h
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srri @$ar0, $ac0.l
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srri @$ar0, $ac1.l
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srri @$ar0, $ac0.m
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srri @$ar0, $ac1.m
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; Regs are stored. Prepare DMA.
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; $cr must be 0x00ff because the ROM uses lrs and srs with the assumption that
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; they will modify hardware registers.
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lri $cr, #0x00ff
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lri $ax0.l, #0x0000
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lri $ax1.l, #1 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
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lri $ax0.h, #0x200
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lr $ac0.l, @MEM_HI
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lr $ac0.m, @MEM_LO
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; Now, why are we looping here?
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lri $ar1, #8+8
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bloop $ar1, dma_copy
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call do_dma
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addi $ac0.m, #0x200
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mrr $ac1.m, $ax0.l
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addi $ac1.m, #0x100
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dma_copy:
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mrr $ax0.l, $ac1.m
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; Wait for the CPU to send us a mail.
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call 0x807e
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si @DMBH, #0x8888
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si @DMBL, #0xfeeb
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si @DIRQ, #0x0001
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; wait for the CPU to recieve our response before we execute the next op
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call 0x8078
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andi $ac0.m, #0x7fff
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lrs $ac1.m, @CMBL
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; Restore all regs again so we're ready to execute another op.
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lri $ar0, #REGS_BASE+1
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lrri $ar1, @$ar0
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lrri $ar2, @$ar0
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lrri $ar3, @$ar0
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lrri $ix0, @$ar0
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lrri $ix1, @$ar0
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lrri $ix2, @$ar0
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lrri $ix3, @$ar0
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; leave $wr for later
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iar $ar0
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lrri $wr1, @$ar0
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lrri $wr2, @$ar0
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lrri $wr3, @$ar0
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lrri $st0, @$ar0
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lrri $st1, @$ar0
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lrri $st2, @$ar0
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lrri $st3, @$ar0
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lrri $ac0.h, @$ar0
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lrri $ac1.h, @$ar0
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lrri $cr, @$ar0
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; leave $sr for later
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iar $ar0
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lrri $prod.l, @$ar0
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lrri $prod.m1, @$ar0
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lrri $prod.h, @$ar0
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lrri $prod.m2, @$ar0
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lrri $ax0.l, @$ar0
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lrri $ax1.l, @$ar0
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lrri $ax0.h, @$ar0
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lrri $ax1.h, @$ar0
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lrri $ac0.l, @$ar0
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lrri $ac1.l, @$ar0
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lrri $ac0.m, @$ar0
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lrri $ac1.m, @$ar0
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lr $ar0, @REGS_BASE
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lr $wr0, @(REGS_BASE+8)
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lr $sr, @(REGS_BASE+19)
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ret ; from send_back
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; Obviously this must be included directly before your test code
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start_of_test:
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; The rest is in dsp_base_noirq.inc
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include "dsp_base_noirq.inc"
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@ -0,0 +1,286 @@
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; This is the trojan program we send to the DSP from DSPSpy to figure it out.
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REGS_BASE: equ 0x0f80
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MEM_HI: equ 0x0f7E
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MEM_LO: equ 0x0f7F
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WARNPC 0x10
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ORG 0x10
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; Main code (and normal entrypoint) at 0x10
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; It is expected that IRQs were listed beforehand
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; (e.g. by including dsp_base.inc instead of dsp_base_noirq.inc)
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sbset #0x02
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sbset #0x03
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sbclr #0x04
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sbset #0x05
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sbset #0x06
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s16
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lri $CR, #0x00ff
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clr $acc1
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clr $acc0
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; get address of memory dump and copy it to DRAM
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call 0x807e
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si @DMBH, #0x8888
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si @DMBL, #0xdead
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si @DIRQ, #0x0001
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call 0x8078
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andi $ac0.m, #0x7fff
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lrs $ac1.m, @CMBL
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sr @MEM_HI, $ac0.m
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sr @MEM_LO, $ac1.m
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lri $ax0.l, #0
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lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
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lri $ax0.h, #0x2000
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lr $ac0.l, @MEM_HI
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lr $ac0.m, @MEM_LO
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call do_dma
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; get address of registers and DMA them to ram
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call 0x807e
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si @DMBH, #0x8888
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si @DMBL, #0xbeef
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si @DIRQ, #0x0001
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call 0x8078
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andi $ac0.m, #0x7fff
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lrs $ac1.m, @CMBL
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sr @MEM_HI, $ac0.m
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sr @MEM_LO, $ac1.m
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lri $ax0.l, #REGS_BASE
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lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
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lri $ax0.h, #0x80
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lr $ac0.l, @MEM_HI
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lr $ac0.m, @MEM_LO
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call do_dma
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; Read in all the registers from RAM
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lri $ar0, #REGS_BASE+1
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lrri $ar1, @$ar0
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lrri $ar2, @$ar0
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lrri $ar3, @$ar0
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lrri $ix0, @$ar0
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lrri $ix1, @$ar0
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lrri $ix2, @$ar0
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lrri $ix3, @$ar0
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lrri $wr0, @$ar0
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lrri $wr1, @$ar0
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lrri $wr2, @$ar0
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lrri $wr3, @$ar0
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lrri $st0, @$ar0
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lrri $st1, @$ar0
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lrri $st2, @$ar0
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lrri $st3, @$ar0
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lrri $ac0.h, @$ar0
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lrri $ac1.h, @$ar0
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lrri $cr, @$ar0
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lrri $sr, @$ar0
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lrri $prod.l, @$ar0
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lrri $prod.m1, @$ar0
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lrri $prod.h, @$ar0
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lrri $prod.m2, @$ar0
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lrri $ax0.l, @$ar0
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lrri $ax1.l, @$ar0
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lrri $ax0.h, @$ar0
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lrri $ax1.h, @$ar0
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lrri $ac0.l, @$ar0
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lrri $ac1.l, @$ar0
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lrri $ac0.m, @$ar0
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lrri $ac1.m, @$ar0
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lr $ar0, @REGS_BASE
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jmp start_of_test
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; This is where we jump when we're done testing, see above.
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; We just fall into a loop, playing dead until someone resets the DSP.
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end_of_test:
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nop
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jmp end_of_test
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; Utility function to do DMA.
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do_dma:
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sr @DSMAH, $ac0.l
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sr @DSMAL, $ac0.m
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sr @DSPA, $ax0.l
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sr @DSCR, $ax1.l
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sr @DSBL, $ax0.h ; This kicks off the DMA.
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wait_dma_finish:
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lr $ac1.m, @DSCR
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andcf $ac1.m, #0x4
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jlz wait_dma_finish
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ret
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; IRQ handlers. Just send back exception# and die
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irq0:
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lri $ac0.m, #0x0000
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jmp irq
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irq1:
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lri $ac0.m, #0x0001
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jmp irq
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irq2:
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lri $ac0.m, #0x0002
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jmp irq
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irq3:
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lri $ac0.m, #0x0003
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jmp irq
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irq4:
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lri $ac0.m, #0x0004
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jmp irq
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irq5:
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lrs $ac0.m, @DMBH
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andcf $ac0.m, #0x8000
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jlz irq5
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si @DMBH, #0x8005
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si @DMBL, #0x0000
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si @DIRQ, #0x0001
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lri $ac0.m, #0xbbbb
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sr @0xffda, $ac0.m ; pred scale
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sr @0xffdb, $ac0.m ; yn1
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lr $ix2, @ARAM
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sr @0xffdc, $ac0.m ; yn2
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rti
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irq6:
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lri $ac0.m, #0x0006
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jmp irq
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irq7:
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lri $ac0.m, #0x0007
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irq:
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lrs $ac1.m, @DMBH
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andcf $ac1.m, #0x8000
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jlz irq
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si @DMBH, #0x8bad
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;sr @DMBL, $wr3 ; ???
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sr @DMBL, $ac0.m ; Exception number
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si @DIRQ, #0x0001
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halt ; Through some magic this allows us to properly ack the exception in dspspy
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;rti ; allow dumping of ucodes which cause exceptions...probably not safe at all
|
||||
|
||||
; DMA:s the current state of the registers back to the PowerPC. To do this,
|
||||
; it must write the contents of all regs to DRAM.
|
||||
send_back:
|
||||
; first, store $sr so we can modify it
|
||||
sr @(REGS_BASE + 19), $sr
|
||||
set16
|
||||
; Now store $wr0, as it must be 0xffff for srri to work as we expect
|
||||
sr @(REGS_BASE + 8), $wr0
|
||||
lri $wr0, #0xffff
|
||||
; store registers to reg table
|
||||
sr @REGS_BASE, $ar0
|
||||
lri $ar0, #(REGS_BASE + 1)
|
||||
srri @$ar0, $ar1
|
||||
srri @$ar0, $ar2
|
||||
srri @$ar0, $ar3
|
||||
srri @$ar0, $ix0
|
||||
srri @$ar0, $ix1
|
||||
srri @$ar0, $ix2
|
||||
srri @$ar0, $ix3
|
||||
; skip $wr0 since we already stored and modified it
|
||||
iar $ar0
|
||||
srri @$ar0, $wr1
|
||||
srri @$ar0, $wr2
|
||||
srri @$ar0, $wr3
|
||||
srri @$ar0, $st0
|
||||
srri @$ar0, $st1
|
||||
srri @$ar0, $st2
|
||||
srri @$ar0, $st3
|
||||
srri @$ar0, $ac0.h
|
||||
srri @$ar0, $ac1.h
|
||||
srri @$ar0, $cr
|
||||
; skip $sr since we already stored and modified it
|
||||
iar $ar0
|
||||
srri @$ar0, $prod.l
|
||||
srri @$ar0, $prod.m1
|
||||
srri @$ar0, $prod.h
|
||||
srri @$ar0, $prod.m2
|
||||
srri @$ar0, $ax0.l
|
||||
srri @$ar0, $ax1.l
|
||||
srri @$ar0, $ax0.h
|
||||
srri @$ar0, $ax1.h
|
||||
srri @$ar0, $ac0.l
|
||||
srri @$ar0, $ac1.l
|
||||
srri @$ar0, $ac0.m
|
||||
srri @$ar0, $ac1.m
|
||||
|
||||
; Regs are stored. Prepare DMA.
|
||||
; $cr must be 0x00ff because the ROM uses lrs and srs with the assumption that
|
||||
; they will modify hardware registers.
|
||||
lri $cr, #0x00ff
|
||||
lri $ax0.l, #0x0000
|
||||
lri $ax1.l, #1 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
|
||||
lri $ax0.h, #0x200
|
||||
lr $ac0.l, @MEM_HI
|
||||
lr $ac0.m, @MEM_LO
|
||||
|
||||
; Now, why are we looping here?
|
||||
lri $ar1, #8+8
|
||||
bloop $ar1, dma_copy
|
||||
call do_dma
|
||||
addi $ac0.m, #0x200
|
||||
mrr $ac1.m, $ax0.l
|
||||
addi $ac1.m, #0x100
|
||||
dma_copy:
|
||||
mrr $ax0.l, $ac1.m
|
||||
|
||||
; Wait for the CPU to send us a mail.
|
||||
call 0x807e
|
||||
si @DMBH, #0x8888
|
||||
si @DMBL, #0xfeeb
|
||||
si @DIRQ, #0x0001
|
||||
|
||||
; wait for the CPU to recieve our response before we execute the next op
|
||||
call 0x8078
|
||||
andi $ac0.m, #0x7fff
|
||||
lrs $ac1.m, @CMBL
|
||||
|
||||
; Restore all regs again so we're ready to execute another op.
|
||||
lri $ar0, #REGS_BASE+1
|
||||
lrri $ar1, @$ar0
|
||||
lrri $ar2, @$ar0
|
||||
lrri $ar3, @$ar0
|
||||
lrri $ix0, @$ar0
|
||||
lrri $ix1, @$ar0
|
||||
lrri $ix2, @$ar0
|
||||
lrri $ix3, @$ar0
|
||||
; leave $wr for later
|
||||
iar $ar0
|
||||
lrri $wr1, @$ar0
|
||||
lrri $wr2, @$ar0
|
||||
lrri $wr3, @$ar0
|
||||
lrri $st0, @$ar0
|
||||
lrri $st1, @$ar0
|
||||
lrri $st2, @$ar0
|
||||
lrri $st3, @$ar0
|
||||
lrri $ac0.h, @$ar0
|
||||
lrri $ac1.h, @$ar0
|
||||
lrri $cr, @$ar0
|
||||
; leave $sr for later
|
||||
iar $ar0
|
||||
lrri $prod.l, @$ar0
|
||||
lrri $prod.m1, @$ar0
|
||||
lrri $prod.h, @$ar0
|
||||
lrri $prod.m2, @$ar0
|
||||
lrri $ax0.l, @$ar0
|
||||
lrri $ax1.l, @$ar0
|
||||
lrri $ax0.h, @$ar0
|
||||
lrri $ax1.h, @$ar0
|
||||
lrri $ac0.l, @$ar0
|
||||
lrri $ac1.l, @$ar0
|
||||
lrri $ac0.m, @$ar0
|
||||
lrri $ac1.m, @$ar0
|
||||
lr $ar0, @REGS_BASE
|
||||
lr $wr0, @(REGS_BASE+8)
|
||||
lr $sr, @(REGS_BASE+19)
|
||||
|
||||
ret ; from send_back
|
||||
|
||||
; Obviously this must be included directly before your test code
|
||||
start_of_test:
|
||||
Loading…
Reference in New Issue