From 5e2fd4520302bd6a7232772ea878894e2b7fed61 Mon Sep 17 00:00:00 2001
From: skidau <skidau@gmail.com>
Date: Tue, 20 Mar 2012 21:01:15 +1100
Subject: [PATCH] Merge fix

---
 Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp    | 42 +++++++++++++++++++
 .../Core/Core/Src/PowerPC/Jit64IL/JitIL.cpp   | 10 +++++
 2 files changed, 52 insertions(+)

diff --git a/Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp b/Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp
index 15bd5ca18a..b43ed516dd 100644
--- a/Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp
+++ b/Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp
@@ -41,6 +41,10 @@
 #include "JitAsm.h"
 #include "JitRegCache.h"
 #include "Jit64_Tables.h"
+#include "HW/ProcessorInterface.h"
+#if defined(_DEBUG) || defined(DEBUGFAST)
+#include "PowerPCDisasm.h"
+#endif
 
 using namespace Gen;
 using namespace PowerPC;
@@ -572,6 +576,44 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
 				SetJumpTarget(b1);
 			}
 
+			// Add an external exception check if the instruction writes to the FIFO.
+			if (jit->js.fifoWriteAddresses.find(ops[i].address) != jit->js.fifoWriteAddresses.end())
+			{
+				gpr.Flush(FLUSH_ALL);
+				fpr.Flush(FLUSH_ALL);
+
+				TEST(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_ISI | EXCEPTION_PROGRAM | EXCEPTION_SYSCALL | EXCEPTION_FPU_UNAVAILABLE | EXCEPTION_DSI | EXCEPTION_ALIGNMENT | EXCEPTION_DECREMENTER));
+				FixupBranch clearInt = J_CC(CC_NZ);
+				TEST(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_EXTERNAL_INT));
+				FixupBranch noExtException = J_CC(CC_Z);
+				TEST(32, M((void *)&PowerPC::ppcState.msr), Imm32(0x0008000));
+				FixupBranch noExtIntEnable = J_CC(CC_Z);
+				TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_CP | ProcessorInterface::INT_CAUSE_PE_TOKEN | ProcessorInterface::INT_CAUSE_PE_FINISH));
+				FixupBranch noCPInt = J_CC(CC_Z);
+
+				MOV(32, M(&PC), Imm32(ops[i].address));
+				WriteExceptionExit();
+
+				SetJumpTarget(noCPInt);
+				SetJumpTarget(noExtIntEnable);
+				SetJumpTarget(noExtException);
+				SetJumpTarget(clearInt);
+			}
+
+			if (Core::g_CoreStartupParameter.bEnableDebugging && breakpoints.IsAddressBreakPoint(ops[i].address) && GetState() != CPU_STEPPING)
+			{
+				MOV(32, M(&PC), Imm32(ops[i].address));
+				ABI_CallFunction(reinterpret_cast<void *>(&PowerPC::CheckBreakPoints));
+				TEST(32, M((void*)PowerPC::GetStatePtr()), Imm32(0xFFFFFFFF));
+				FixupBranch noBreakpoint = J_CC(CC_Z);
+
+				gpr.Flush(FLUSH_ALL);
+				fpr.Flush(FLUSH_ALL);
+
+				WriteExit(ops[i].address, 0);
+				SetJumpTarget(noBreakpoint);
+			}
+
 			Jit64Tables::CompileInstruction(ops[i]);
 
 			if (js.memcheck && (opinfo->flags & FL_LOADSTORE))
diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL.cpp
index 0c6fc41366..e079fb7896 100644
--- a/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL.cpp
+++ b/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL.cpp
@@ -652,6 +652,16 @@ const u8* JitIL::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
 			{
 				ibuild.EmitFPExceptionCheckStart(ibuild.EmitIntConst(ops[i].address));
 			}
+
+			if (jit->js.fifoWriteAddresses.find(js.compilerPC) != jit->js.fifoWriteAddresses.end())
+			{
+				ibuild.EmitExtExceptionCheck(ibuild.EmitIntConst(ops[i].address));
+			}
+
+			if (Core::g_CoreStartupParameter.bEnableDebugging && breakpoints.IsAddressBreakPoint(ops[i].address) && GetState() != CPU_STEPPING)
+			{
+				ibuild.EmitBreakPointCheck(ibuild.EmitIntConst(ops[i].address));
+			}
 			
 			JitILTables::CompileInstruction(ops[i]);