[AArch64] Implement {U, S}QXTN{,2}
Also split out XTN to XTN and XTN2.
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@ -3131,10 +3131,29 @@ void ARM64FloatEmitter::UCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn, int scale)
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int imm = size * 2 - scale;
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int imm = size * 2 - scale;
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EmitShiftImm(IsQuad(Rd), 1, imm >> 3, imm & 7, 0x1C, Rd, Rn);
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EmitShiftImm(IsQuad(Rd), 1, imm >> 3, imm & 7, 0x1C, Rd, Rn);
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}
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}
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void ARM64FloatEmitter::SQXTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn)
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{
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Emit2RegMisc(false, 0, dest_size >> 4, 0b10100, Rd, Rn);
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}
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void ARM64FloatEmitter::SQXTN2(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn)
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{
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Emit2RegMisc(true, 0, dest_size >> 4, 0b10100, Rd, Rn);
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}
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void ARM64FloatEmitter::UQXTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn)
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{
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Emit2RegMisc(false, 1, dest_size >> 4, 0b10100, Rd, Rn);
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}
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void ARM64FloatEmitter::UQXTN2(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn)
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{
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Emit2RegMisc(true, 1, dest_size >> 4, 0b10100, Rd, Rn);
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}
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void ARM64FloatEmitter::XTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn)
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void ARM64FloatEmitter::XTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn)
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{
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{
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Emit2RegMisc(IsQuad(Rd), 0, dest_size >> 4, 0x12, Rd, Rn);
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Emit2RegMisc(false, 0, dest_size >> 4, 0b10010, Rd, Rn);
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}
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void ARM64FloatEmitter::XTN2(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn)
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{
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Emit2RegMisc(true, 0, dest_size >> 4, 0b10010, Rd, Rn);
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}
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}
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// Move
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// Move
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@ -829,7 +829,12 @@ public:
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void UCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void UCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void SCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn, int scale);
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void SCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn, int scale);
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void UCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn, int scale);
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void UCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn, int scale);
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void SQXTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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void SQXTN2(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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void UQXTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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void UQXTN2(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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void XTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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void XTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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void XTN2(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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// Move
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// Move
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void DUP(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void DUP(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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