Qt/Debugger: Add TB, XER and GQRs to Registers Window
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dc08b73db1
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5cff714b77
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@ -96,13 +96,13 @@ void RegisterColumn::Update()
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switch (m_display)
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switch (m_display)
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{
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{
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case RegisterDisplay::Hex:
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case RegisterDisplay::Hex:
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text = QStringLiteral("%1").arg(m_value,
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text = QStringLiteral("%1").arg(
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(m_type == RegisterType::ibat || m_type == RegisterType::dbat ||
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m_value, (m_type == RegisterType::ibat || m_type == RegisterType::dbat ||
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m_type == RegisterType::fpr ?
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m_type == RegisterType::fpr || m_type == RegisterType::tb ?
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sizeof(u64) :
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sizeof(u64) :
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sizeof(u32)) *
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sizeof(u32)) *
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2,
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2,
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16, QLatin1Char('0'));
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16, QLatin1Char('0'));
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break;
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break;
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case RegisterDisplay::SInt32:
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case RegisterDisplay::SInt32:
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text = QString::number(static_cast<qint32>(m_value));
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text = QString::number(static_cast<qint32>(m_value));
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@ -16,14 +16,17 @@ enum class RegisterType
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fpr, // General purpose registers, float (f0-f31)
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fpr, // General purpose registers, float (f0-f31)
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ibat, // Instruction BATs (IBAT0-IBAT7)
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ibat, // Instruction BATs (IBAT0-IBAT7)
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dbat, // Data BATs (DBAT0-DBAT7)
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dbat, // Data BATs (DBAT0-DBAT7)
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tb, // Time base register
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pc, // Program counter
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pc, // Program counter
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lr, // Link register
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lr, // Link register
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ctr, // Decremented and incremented by branch and count instructions
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ctr, // Decremented and incremented by branch and count instructions
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cr, // Condition register
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cr, // Condition register
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xer, // Integer exception register
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fpscr, // Floating point status and control register
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fpscr, // Floating point status and control register
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msr, // Machine state register
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msr, // Machine state register
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srr, // Machine status save/restore register (SRR0 - SRR1)
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srr, // Machine status save/restore register (SRR0 - SRR1)
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sr, // Segment register (SR0 - SR15)
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sr, // Segment register (SR0 - SR15)
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gqr, // Graphics quantization registers (GQR0 - GQR7)
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exceptions, // Keeps track of currently triggered exceptions
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exceptions, // Keeps track of currently triggered exceptions
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int_mask, // ???
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int_mask, // ???
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int_cause, // ???
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int_cause, // ???
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@ -236,6 +236,9 @@ void RegisterWidget::PopulateTable()
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PowerPC::ppcState.spr[SPR_DBAT0L + i * 2];
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PowerPC::ppcState.spr[SPR_DBAT0L + i * 2];
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},
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},
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nullptr);
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nullptr);
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// Graphics quantization registers
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AddRegister(i + 16, 7, RegisterType::gqr, "GQR" + std::to_string(i),
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[i] { return PowerPC::ppcState.spr[SPR_GQR0 + i]; }, nullptr);
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}
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}
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for (int i = 0; i < 16; i++)
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for (int i = 0; i < 16; i++)
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@ -247,59 +250,71 @@ void RegisterWidget::PopulateTable()
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}
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}
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// Special registers
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// Special registers
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// TB
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AddRegister(16, 5, RegisterType::tb, "TB",
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[] {
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return static_cast<u64>(PowerPC::ppcState.spr[SPR_TU]) << 32 |
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PowerPC::ppcState.spr[SPR_TL];
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},
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nullptr);
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// PC
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// PC
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AddRegister(16, 5, RegisterType::pc, "PC", [] { return PowerPC::ppcState.pc; },
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AddRegister(17, 5, RegisterType::pc, "PC", [] { return PowerPC::ppcState.pc; },
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[](u64 value) { PowerPC::ppcState.pc = value; });
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[](u64 value) { PowerPC::ppcState.pc = value; });
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// LR
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// LR
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AddRegister(17, 5, RegisterType::fpscr, "LR", [] { return PowerPC::ppcState.spr[SPR_LR]; },
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AddRegister(18, 5, RegisterType::lr, "LR", [] { return PowerPC::ppcState.spr[SPR_LR]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_LR] = value; });
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[](u64 value) { PowerPC::ppcState.spr[SPR_LR] = value; });
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// CTR
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// CTR
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AddRegister(18, 5, RegisterType::fpscr, "FPSCR", [] { return PowerPC::ppcState.spr[SPR_CTR]; },
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AddRegister(19, 5, RegisterType::ctr, "CTR", [] { return PowerPC::ppcState.spr[SPR_CTR]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_CTR] = value; });
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[](u64 value) { PowerPC::ppcState.spr[SPR_CTR] = value; });
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// CR
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// CR
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AddRegister(19, 5, RegisterType::cr, "CR", [] { return GetCR(); },
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AddRegister(20, 5, RegisterType::cr, "CR", [] { return GetCR(); },
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[](u64 value) { SetCR(value); });
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[](u64 value) { SetCR(value); });
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// XER
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AddRegister(21, 5, RegisterType::xer, "XER", [] { return GetXER().Hex; },
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[](u64 value) { SetXER(UReg_XER(value)); });
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// FPSCR
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// FPSCR
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AddRegister(20, 5, RegisterType::fpscr, "FPSCR", [] { return PowerPC::ppcState.fpscr; },
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AddRegister(22, 5, RegisterType::fpscr, "FPSCR", [] { return PowerPC::ppcState.fpscr; },
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[](u64 value) { PowerPC::ppcState.fpscr = value; });
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[](u64 value) { PowerPC::ppcState.fpscr = value; });
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// MSR
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// MSR
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AddRegister(21, 5, RegisterType::msr, "MSR", [] { return PowerPC::ppcState.msr; },
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AddRegister(23, 5, RegisterType::msr, "MSR", [] { return PowerPC::ppcState.msr; },
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[](u64 value) { PowerPC::ppcState.msr = value; });
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[](u64 value) { PowerPC::ppcState.msr = value; });
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// SRR 0-1
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// SRR 0-1
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AddRegister(22, 5, RegisterType::srr, "SRR0", [] { return PowerPC::ppcState.spr[SPR_SRR0]; },
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AddRegister(24, 5, RegisterType::srr, "SRR0", [] { return PowerPC::ppcState.spr[SPR_SRR0]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_SRR0] = value; });
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[](u64 value) { PowerPC::ppcState.spr[SPR_SRR0] = value; });
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AddRegister(23, 5, RegisterType::srr, "SRR1", [] { return PowerPC::ppcState.spr[SPR_SRR1]; },
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AddRegister(25, 5, RegisterType::srr, "SRR1", [] { return PowerPC::ppcState.spr[SPR_SRR1]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_SRR1] = value; });
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[](u64 value) { PowerPC::ppcState.spr[SPR_SRR1] = value; });
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// Exceptions
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// Exceptions
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AddRegister(24, 5, RegisterType::exceptions, "Exceptions",
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AddRegister(26, 5, RegisterType::exceptions, "Exceptions",
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[] { return PowerPC::ppcState.Exceptions; },
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[] { return PowerPC::ppcState.Exceptions; },
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[](u64 value) { PowerPC::ppcState.Exceptions = value; });
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[](u64 value) { PowerPC::ppcState.Exceptions = value; });
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// Int Mask
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// Int Mask
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AddRegister(25, 5, RegisterType::int_mask, "Int Mask",
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AddRegister(27, 5, RegisterType::int_mask, "Int Mask",
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[] { return ProcessorInterface::GetMask(); }, nullptr);
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[] { return ProcessorInterface::GetMask(); }, nullptr);
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// Int Cause
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// Int Cause
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AddRegister(26, 5, RegisterType::int_cause, "Int Cause",
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AddRegister(28, 5, RegisterType::int_cause, "Int Cause",
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[] { return ProcessorInterface::GetCause(); }, nullptr);
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[] { return ProcessorInterface::GetCause(); }, nullptr);
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// DSISR
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// DSISR
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AddRegister(27, 5, RegisterType::dsisr, "DSISR", [] { return PowerPC::ppcState.spr[SPR_DSISR]; },
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AddRegister(29, 5, RegisterType::dsisr, "DSISR", [] { return PowerPC::ppcState.spr[SPR_DSISR]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_DSISR] = value; });
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[](u64 value) { PowerPC::ppcState.spr[SPR_DSISR] = value; });
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// DAR
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// DAR
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AddRegister(28, 5, RegisterType::dar, "DAR", [] { return PowerPC::ppcState.spr[SPR_DAR]; },
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AddRegister(30, 5, RegisterType::dar, "DAR", [] { return PowerPC::ppcState.spr[SPR_DAR]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_DAR] = value; });
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[](u64 value) { PowerPC::ppcState.spr[SPR_DAR] = value; });
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// Hash Mask
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// Hash Mask
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AddRegister(
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AddRegister(
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29, 5, RegisterType::pt_hashmask, "Hash Mask",
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31, 5, RegisterType::pt_hashmask, "Hash Mask",
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[] { return (PowerPC::ppcState.pagetable_hashmask << 6) | PowerPC::ppcState.pagetable_base; },
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[] { return (PowerPC::ppcState.pagetable_hashmask << 6) | PowerPC::ppcState.pagetable_base; },
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nullptr);
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nullptr);
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