Merge pull request #11147 from JosJuice/jitarm64-arith-org
JitArm64: Merge ps_mulsX, ps_maddXX, and parts of fp_arith
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commit
5b69c67b3a
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@ -152,9 +152,8 @@ public:
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void frsqrtex(UGeckoInstruction inst);
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// Paired
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void ps_maddXX(UGeckoInstruction inst);
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void ps_mergeXX(UGeckoInstruction inst);
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void ps_mulsX(UGeckoInstruction inst);
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void ps_arith(UGeckoInstruction inst);
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void ps_sel(UGeckoInstruction inst);
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void ps_sumX(UGeckoInstruction inst);
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void ps_res(UGeckoInstruction inst);
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@ -69,86 +69,35 @@ void JitArm64::fp_arith(UGeckoInstruction inst)
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u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
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u32 op5 = inst.SUBOP5;
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bool single = inst.OPCD == 59;
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bool packed = inst.OPCD == 4;
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const bool use_c = op5 >= 25; // fmul and all kind of fmaddXX
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const bool use_b = op5 != 25; // fmul uses no B
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const bool outputs_are_singles = single || packed;
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const bool round_c = use_c && outputs_are_singles && !js.op->fprIsSingle[inst.FC];
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const bool output_is_single = inst.OPCD == 59;
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const bool inaccurate_fma = op5 > 25 && !Config::Get(Config::SESSION_USE_FMA);
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const bool round_c = use_c && output_is_single && !js.op->fprIsSingle[inst.FC];
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const auto inputs_are_singles_func = [&] {
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return fpr.IsSingle(a, !packed) && (!use_b || fpr.IsSingle(b, !packed)) &&
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(!use_c || fpr.IsSingle(c, !packed));
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return fpr.IsSingle(a, true) && (!use_b || fpr.IsSingle(b, true)) &&
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(!use_c || fpr.IsSingle(c, true));
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};
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const bool inputs_are_singles = inputs_are_singles_func();
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ARM64Reg VA{}, VB{}, VC{}, VD{};
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const RegType type =
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(inputs_are_singles && output_is_single) ? RegType::LowerPairSingle : RegType::LowerPair;
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const RegType type_out =
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output_is_single ? (inputs_are_singles ? RegType::DuplicatedSingle : RegType::Duplicated) :
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RegType::LowerPair;
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const auto reg_encoder =
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(inputs_are_singles && output_is_single) ? EncodeRegToSingle : EncodeRegToDouble;
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const ARM64Reg VA = reg_encoder(fpr.R(a, type));
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const ARM64Reg VB = use_b ? reg_encoder(fpr.R(b, type)) : ARM64Reg::INVALID_REG;
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ARM64Reg VC = use_c ? reg_encoder(fpr.R(c, type)) : ARM64Reg::INVALID_REG;
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const ARM64Reg VD = reg_encoder(fpr.RW(d, type_out));
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ARM64Reg V0Q = ARM64Reg::INVALID_REG;
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ARM64Reg V1Q = ARM64Reg::INVALID_REG;
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if (packed)
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{
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const RegType type = inputs_are_singles ? RegType::Single : RegType::Register;
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const u8 size = inputs_are_singles ? 32 : 64;
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const auto reg_encoder = inputs_are_singles ? EncodeRegToDouble : EncodeRegToQuad;
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VA = reg_encoder(fpr.R(a, type));
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if (use_b)
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VB = reg_encoder(fpr.R(b, type));
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if (use_c)
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VC = reg_encoder(fpr.R(c, type));
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VD = reg_encoder(fpr.RW(d, type));
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if (round_c)
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{
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ASSERT_MSG(DYNA_REC, !inputs_are_singles, "Tried to apply 25-bit precision to single");
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V0Q = fpr.GetReg();
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Force25BitPrecision(reg_encoder(V0Q), VC);
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VC = reg_encoder(V0Q);
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}
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switch (op5)
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{
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case 18:
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m_float_emit.FDIV(size, VD, VA, VB);
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break;
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case 20:
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m_float_emit.FSUB(size, VD, VA, VB);
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break;
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case 21:
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m_float_emit.FADD(size, VD, VA, VB);
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break;
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case 25:
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m_float_emit.FMUL(size, VD, VA, VC);
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break;
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default:
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ASSERT_MSG(DYNA_REC, 0, "fp_arith");
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break;
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}
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}
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else
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{
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const RegType type =
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(inputs_are_singles && single) ? RegType::LowerPairSingle : RegType::LowerPair;
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const RegType type_out =
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single ? (inputs_are_singles ? RegType::DuplicatedSingle : RegType::Duplicated) :
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RegType::LowerPair;
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const auto reg_encoder = (inputs_are_singles && single) ? EncodeRegToSingle : EncodeRegToDouble;
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VA = reg_encoder(fpr.R(a, type));
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if (use_b)
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VB = reg_encoder(fpr.R(b, type));
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if (use_c)
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VC = reg_encoder(fpr.R(c, type));
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VD = reg_encoder(fpr.RW(d, type_out));
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const bool inaccurate_fma = op5 > 25 && !Config::Get(Config::SESSION_USE_FMA);
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if (round_c)
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{
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ASSERT_MSG(DYNA_REC, !inputs_are_singles, "Tried to apply 25-bit precision to single");
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@ -217,14 +166,13 @@ void JitArm64::fp_arith(UGeckoInstruction inst)
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ASSERT_MSG(DYNA_REC, 0, "fp_arith");
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break;
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}
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}
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if (V0Q != ARM64Reg::INVALID_REG)
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fpr.Unlock(V0Q);
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if (V1Q != ARM64Reg::INVALID_REG)
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fpr.Unlock(V1Q);
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if (outputs_are_singles)
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if (output_is_single)
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{
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ASSERT_MSG(DYNA_REC, inputs_are_singles == inputs_are_singles_func(),
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"Register allocation turned singles into doubles in the middle of fp_arith");
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@ -232,7 +180,7 @@ void JitArm64::fp_arith(UGeckoInstruction inst)
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fpr.FixSinglePrecision(d);
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}
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SetFPRFIfNeeded(outputs_are_singles, VD);
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SetFPRFIfNeeded(output_is_single, VD);
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}
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void JitArm64::fp_logic(UGeckoInstruction inst)
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@ -73,55 +73,7 @@ void JitArm64::ps_mergeXX(UGeckoInstruction inst)
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"Register allocation turned singles into doubles in the middle of ps_mergeXX");
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}
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void JitArm64::ps_mulsX(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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FALLBACK_IF(jo.fp_exceptions);
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const u32 a = inst.FA;
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const u32 c = inst.FC;
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const u32 d = inst.FD;
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const bool upper = inst.SUBOP5 == 13;
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const bool singles = fpr.IsSingle(a) && fpr.IsSingle(c);
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const bool round_c = !js.op->fprIsSingle[inst.FC];
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const RegType type = singles ? RegType::Single : RegType::Register;
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const u8 size = singles ? 32 : 64;
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const auto reg_encoder = singles ? EncodeRegToDouble : EncodeRegToQuad;
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const ARM64Reg VA = fpr.R(a, type);
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ARM64Reg VC = fpr.R(c, type);
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const ARM64Reg VD = fpr.RW(d, type);
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ARM64Reg V0Q = ARM64Reg::INVALID_REG;
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if (round_c)
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{
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ASSERT_MSG(DYNA_REC, !singles, "Tried to apply 25-bit precision to single");
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V0Q = fpr.GetReg();
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Force25BitPrecision(reg_encoder(V0Q), reg_encoder(VC));
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VC = reg_encoder(V0Q);
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}
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m_float_emit.FMUL(size, reg_encoder(VD), reg_encoder(VA), reg_encoder(VC), upper ? 1 : 0);
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if (V0Q != ARM64Reg::INVALID_REG)
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fpr.Unlock(V0Q);
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ASSERT_MSG(DYNA_REC, singles == (fpr.IsSingle(a) && fpr.IsSingle(c)),
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"Register allocation turned singles into doubles in the middle of ps_mulsX");
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fpr.FixSinglePrecision(d);
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SetFPRFIfNeeded(true, VD);
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}
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void JitArm64::ps_maddXX(UGeckoInstruction inst)
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void JitArm64::ps_arith(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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@ -134,16 +86,23 @@ void JitArm64::ps_maddXX(UGeckoInstruction inst)
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const u32 d = inst.FD;
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const u32 op5 = inst.SUBOP5;
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const bool use_c = op5 == 25 || (op5 & ~0x13) == 12; // mul, muls, and all kinds of maddXX
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const bool use_b = op5 != 25 && (op5 & ~0x1) != 12; // mul and muls don't use B
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const auto singles_func = [&] {
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return fpr.IsSingle(a) && (!use_b || fpr.IsSingle(b)) && (!use_c || fpr.IsSingle(c));
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};
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const bool singles = singles_func();
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const bool inaccurate_fma = !Config::Get(Config::SESSION_USE_FMA);
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const bool singles = fpr.IsSingle(a) && fpr.IsSingle(b) && fpr.IsSingle(c);
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const bool round_c = !js.op->fprIsSingle[inst.FC];
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const bool round_c = use_c && !js.op->fprIsSingle[inst.FC];
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const RegType type = singles ? RegType::Single : RegType::Register;
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const u8 size = singles ? 32 : 64;
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const auto reg_encoder = singles ? EncodeRegToDouble : EncodeRegToQuad;
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const ARM64Reg VA = reg_encoder(fpr.R(a, type));
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const ARM64Reg VB = reg_encoder(fpr.R(b, type));
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ARM64Reg VC = reg_encoder(fpr.R(c, type));
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const ARM64Reg VB = use_b ? reg_encoder(fpr.R(b, type)) : ARM64Reg::INVALID_REG;
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ARM64Reg VC = use_c ? reg_encoder(fpr.R(c, type)) : ARM64Reg::INVALID_REG;
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const ARM64Reg VD = reg_encoder(fpr.RW(d, type));
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ARM64Reg V0Q = ARM64Reg::INVALID_REG;
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@ -178,6 +137,12 @@ void JitArm64::ps_maddXX(UGeckoInstruction inst)
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ARM64Reg result_reg = VD;
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switch (op5)
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{
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case 12: // ps_muls0: d = a * c.ps0
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m_float_emit.FMUL(size, VD, VA, VC, 0);
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break;
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case 13: // ps_muls1: d = a * c.ps1
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m_float_emit.FMUL(size, VD, VA, VC, 1);
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break;
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case 14: // ps_madds0: d = a * c.ps0 + b
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if (inaccurate_fma)
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{
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@ -224,6 +189,18 @@ void JitArm64::ps_maddXX(UGeckoInstruction inst)
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result_reg = V0;
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}
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break;
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case 18: // ps_div
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m_float_emit.FDIV(size, VD, VA, VB);
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break;
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case 20: // ps_sub
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m_float_emit.FSUB(size, VD, VA, VB);
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break;
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case 21: // ps_add
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m_float_emit.FADD(size, VD, VA, VB);
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break;
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case 25: // ps_mul
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m_float_emit.FMUL(size, VD, VA, VC);
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break;
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case 28: // ps_msub: d = a * c - b
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case 30: // ps_nmsub: d = -(a * c - b)
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if (inaccurate_fma)
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@ -269,7 +246,7 @@ void JitArm64::ps_maddXX(UGeckoInstruction inst)
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}
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break;
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default:
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ASSERT_MSG(DYNA_REC, 0, "ps_madd - invalid op");
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ASSERT_MSG(DYNA_REC, 0, "ps_arith - invalid op");
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break;
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}
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@ -292,8 +269,8 @@ void JitArm64::ps_maddXX(UGeckoInstruction inst)
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if (V1Q != ARM64Reg::INVALID_REG)
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fpr.Unlock(V1Q);
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ASSERT_MSG(DYNA_REC, singles == (fpr.IsSingle(a) && fpr.IsSingle(b) && fpr.IsSingle(c)),
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"Register allocation turned singles into doubles in the middle of ps_maddXX");
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ASSERT_MSG(DYNA_REC, singles == singles_func(),
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"Register allocation turned singles into doubles in the middle of ps_arith");
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fpr.FixSinglePrecision(d);
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@ -108,21 +108,21 @@ constexpr std::array<GekkoOPTemplate, 13> table4{{
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constexpr std::array<GekkoOPTemplate, 17> table4_2{{
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{10, &JitArm64::ps_sumX}, // ps_sum0
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{11, &JitArm64::ps_sumX}, // ps_sum1
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{12, &JitArm64::ps_mulsX}, // ps_muls0
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{13, &JitArm64::ps_mulsX}, // ps_muls1
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{14, &JitArm64::ps_maddXX}, // ps_madds0
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{15, &JitArm64::ps_maddXX}, // ps_madds1
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{18, &JitArm64::fp_arith}, // ps_div
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{20, &JitArm64::fp_arith}, // ps_sub
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{21, &JitArm64::fp_arith}, // ps_add
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{12, &JitArm64::ps_arith}, // ps_muls0
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{13, &JitArm64::ps_arith}, // ps_muls1
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{14, &JitArm64::ps_arith}, // ps_madds0
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{15, &JitArm64::ps_arith}, // ps_madds1
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{18, &JitArm64::ps_arith}, // ps_div
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{20, &JitArm64::ps_arith}, // ps_sub
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{21, &JitArm64::ps_arith}, // ps_add
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{23, &JitArm64::ps_sel}, // ps_sel
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{24, &JitArm64::ps_res}, // ps_res
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{25, &JitArm64::fp_arith}, // ps_mul
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{25, &JitArm64::ps_arith}, // ps_mul
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{26, &JitArm64::ps_rsqrte}, // ps_rsqrte
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{28, &JitArm64::ps_maddXX}, // ps_msub
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{29, &JitArm64::ps_maddXX}, // ps_madd
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{30, &JitArm64::ps_maddXX}, // ps_nmsub
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{31, &JitArm64::ps_maddXX}, // ps_nmadd
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{28, &JitArm64::ps_arith}, // ps_msub
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{29, &JitArm64::ps_arith}, // ps_madd
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{30, &JitArm64::ps_arith}, // ps_nmsub
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{31, &JitArm64::ps_arith}, // ps_nmadd
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}};
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constexpr std::array<GekkoOPTemplate, 4> table4_3{{
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