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JitArm64: Use immediates more in fres routine 

Not sure why I didn't do this to begin with. Maybe I was under the
impression that the most significant bit of a 12-bit immediate was a
sign bit.
This commit is contained in:
JosJuice 2023-06-14 23:27:58 +02:00
parent 89e7e7d669
commit 5b5124d9ff
1 changed files with 2 additions and 4 deletions
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6
Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
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@ -287,8 +287,7 @@ void JitArm64::GenerateFres()
CMP(ARM64Reg::X2, 895); CMP(ARM64Reg::X2, 895);
FixupBranch small_exponent = B(CCFlags::CC_LO); FixupBranch small_exponent = B(CCFlags::CC_LO);
MOVI2R(ARM64Reg::X4, 1148LL); CMP(ARM64Reg::X2, 1148);
CMP(ARM64Reg::X2, ARM64Reg::X4);
FixupBranch large_exponent = B(CCFlags::CC_HI); FixupBranch large_exponent = B(CCFlags::CC_HI);
UBFX(ARM64Reg::X2, ARM64Reg::X1, 47, 5); // Grab upper part of mantissa UBFX(ARM64Reg::X2, ARM64Reg::X1, 47, 5); // Grab upper part of mantissa
@ -320,8 +319,7 @@ void JitArm64::GenerateFres()
RET(); RET();
SetJumpTarget(large_exponent); SetJumpTarget(large_exponent);
MOVI2R(ARM64Reg::X4, 0x7FF); CMP(ARM64Reg::X2, 0x7FF);
CMP(ARM64Reg::X2, ARM64Reg::X4);
CSEL(ARM64Reg::X0, ARM64Reg::X0, ARM64Reg::X3, CCFlags::CC_EQ); CSEL(ARM64Reg::X0, ARM64Reg::X0, ARM64Reg::X3, CCFlags::CC_EQ);
RET(); RET();
} }