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[AArch64] Add a few more VFP register helpers. 

Renames Is128Bit to IsQuad to line up more with the other helpers.
This commit is contained in:
Ryan Houdek 2015-01-07 13:05:55 -06:00
parent 2b4f1aed40
commit 5a0133c478
2 changed files with 4 additions and 2 deletions
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2
Source/Core/Common/Arm64Emitter.cpp
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@ -377,7 +377,7 @@ void ARM64XEmitter::EncodeLoadStoreExcInst(u32 instenc,
void ARM64XEmitter::EncodeLoadStorePairedInst(u32 op, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, u32 imm) void ARM64XEmitter::EncodeLoadStorePairedInst(u32 op, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, u32 imm)
{ {
bool b64Bit = Is64Bit(Rt); bool b64Bit = Is64Bit(Rt);
bool b128Bit = Is128Bit(Rt); bool b128Bit = IsQuad(Rt);
bool bVec = IsVector(Rt); bool bVec = IsVector(Rt);
if (b128Bit) if (b128Bit)

4
Source/Core/Common/Arm64Emitter.h
View File

@ -76,7 +76,9 @@ enum ARM64Reg
}; };
inline bool Is64Bit(ARM64Reg reg) { return reg & 0x20; } inline bool Is64Bit(ARM64Reg reg) { return reg & 0x20; }
inline bool Is128Bit(ARM64Reg reg) { return reg & 0xC0; } inline bool IsSingle(ARM64Reg reg) { return reg & 0x40; }
inline bool IsDouble(ARM64Reg reg) { return reg & 0x80; }
inline bool IsQuad(ARM64Reg reg) { return (reg & 0xC0) == 0xC0; }
inline bool IsVector(ARM64Reg reg) { return (reg & 0xC0) != 0; } inline bool IsVector(ARM64Reg reg) { return (reg & 0xC0) != 0; }
inline ARM64Reg DecodeReg(ARM64Reg reg) { return (ARM64Reg)(reg & 0x1F); } inline ARM64Reg DecodeReg(ARM64Reg reg) { return (ARM64Reg)(reg & 0x1F); }
inline ARM64Reg EncodeRegTo64(ARM64Reg reg) { return (ARM64Reg)(reg | 0x20); } inline ARM64Reg EncodeRegTo64(ARM64Reg reg) { return (ARM64Reg)(reg | 0x20); }