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JitArm64_Integer: extract bit operation lambdas 

Fixes warnings like:

```
dolphin/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp:132:37: warning: declaration shadows a local variable [-Wshadow]
    reg_imm(a, s, inst.UIMM, [](u32 a, u32 b) { return a | b; }, &ARM64XEmitter::ORRI2R);
                                    ^
/Users/michaelmaltese/Downloads/dolphin/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp:122:7: note: previous declaration is here
  u32 a = inst.RA, s = inst.RS;
      ^
```
This commit is contained in:
Michael Maltese 2017-03-25 14:04:53 -07:00
parent 3d7bace9da
commit 5892ef1792
1 changed files with 21 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
View File

@ -115,6 +115,21 @@ void JitArm64::reg_imm(u32 d, u32 a, u32 value, u32 (*do_op)(u32, u32),
} }
} }
static constexpr u32 BitOR(u32 a, u32 b)
{
return a | b;
}
static constexpr u32 BitAND(u32 a, u32 b)
{
return a & b;
}
static constexpr u32 BitXOR(u32 a, u32 b)
{
return a ^ b;
}
void JitArm64::arith_imm(UGeckoInstruction inst) void JitArm64::arith_imm(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
@ -129,23 +144,22 @@ void JitArm64::arith_imm(UGeckoInstruction inst)
// NOP // NOP
return; return;
} }
reg_imm(a, s, inst.UIMM, [](u32 a, u32 b) { return a | b; }, &ARM64XEmitter::ORRI2R); reg_imm(a, s, inst.UIMM, BitOR, &ARM64XEmitter::ORRI2R);
break; break;
case 25: // oris case 25: // oris
reg_imm(a, s, inst.UIMM << 16, [](u32 a, u32 b) { return a | b; }, &ARM64XEmitter::ORRI2R); reg_imm(a, s, inst.UIMM << 16, BitOR, &ARM64XEmitter::ORRI2R);
break; break;
case 28: // andi case 28: // andi
reg_imm(a, s, inst.UIMM, [](u32 a, u32 b) { return a & b; }, &ARM64XEmitter::ANDI2R, true); reg_imm(a, s, inst.UIMM, BitAND, &ARM64XEmitter::ANDI2R, true);
break; break;
case 29: // andis case 29: // andis
reg_imm(a, s, inst.UIMM << 16, [](u32 a, u32 b) { return a & b; }, &ARM64XEmitter::ANDI2R, reg_imm(a, s, inst.UIMM << 16, BitAND, &ARM64XEmitter::ANDI2R, true);
true);
break; break;
case 26: // xori case 26: // xori
reg_imm(a, s, inst.UIMM, [](u32 a, u32 b) { return a ^ b; }, &ARM64XEmitter::EORI2R); reg_imm(a, s, inst.UIMM, BitXOR, &ARM64XEmitter::EORI2R);
break; break;
case 27: // xoris case 27: // xoris
reg_imm(a, s, inst.UIMM << 16, [](u32 a, u32 b) { return a ^ b; }, &ARM64XEmitter::EORI2R); reg_imm(a, s, inst.UIMM << 16, BitXOR, &ARM64XEmitter::EORI2R);
break; break;
} }
} }