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Merge pull request #6293 from container1234/dolphinqt-debugger 

Qt/Debugger: Add TB, XER and GQRs to Registers Window
This commit is contained in:
Anthony 2018-01-09 21:25:17 -05:00 committed by GitHub
parent 22f469697b 5cff714b77
commit 57640a4c83
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 39 additions and 21 deletions
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14
Source/Core/DolphinQt2/Debugger/RegisterColumn.cpp
View File

@ -96,13 +96,13 @@ void RegisterColumn::Update()
switch (m_display) switch (m_display)
{ {
case RegisterDisplay::Hex: case RegisterDisplay::Hex:
text = QStringLiteral("%1").arg(m_value, text = QStringLiteral("%1").arg(
(m_type == RegisterType::ibat || m_type == RegisterType::dbat || m_value, (m_type == RegisterType::ibat || m_type == RegisterType::dbat ||
m_type == RegisterType::fpr ? m_type == RegisterType::fpr || m_type == RegisterType::tb ?
sizeof(u64) : sizeof(u64) :
sizeof(u32)) * sizeof(u32)) *
2, 2,
16, QLatin1Char('0')); 16, QLatin1Char('0'));
break; break;
case RegisterDisplay::SInt32: case RegisterDisplay::SInt32:
text = QString::number(static_cast<qint32>(m_value)); text = QString::number(static_cast<qint32>(m_value));

3
Source/Core/DolphinQt2/Debugger/RegisterColumn.h
View File

@ -16,14 +16,17 @@ enum class RegisterType
fpr, // General purpose registers, float (f0-f31) fpr, // General purpose registers, float (f0-f31)
ibat, // Instruction BATs (IBAT0-IBAT7) ibat, // Instruction BATs (IBAT0-IBAT7)
dbat, // Data BATs (DBAT0-DBAT7) dbat, // Data BATs (DBAT0-DBAT7)
tb, // Time base register
pc, // Program counter pc, // Program counter
lr, // Link register lr, // Link register
ctr, // Decremented and incremented by branch and count instructions ctr, // Decremented and incremented by branch and count instructions
cr, // Condition register cr, // Condition register
xer, // Integer exception register
fpscr, // Floating point status and control register fpscr, // Floating point status and control register
msr, // Machine state register msr, // Machine state register
srr, // Machine status save/restore register (SRR0 - SRR1) srr, // Machine status save/restore register (SRR0 - SRR1)
sr, // Segment register (SR0 - SR15) sr, // Segment register (SR0 - SR15)
gqr, // Graphics quantization registers (GQR0 - GQR7)
exceptions, // Keeps track of currently triggered exceptions exceptions, // Keeps track of currently triggered exceptions
int_mask, // ??? int_mask, // ???
int_cause, // ??? int_cause, // ???

43
Source/Core/DolphinQt2/Debugger/RegisterWidget.cpp
View File

@ -236,6 +236,9 @@ void RegisterWidget::PopulateTable()
PowerPC::ppcState.spr[SPR_DBAT0L + i * 2]; PowerPC::ppcState.spr[SPR_DBAT0L + i * 2];
}, },
nullptr); nullptr);
// Graphics quantization registers
AddRegister(i + 16, 7, RegisterType::gqr, "GQR" + std::to_string(i),
[i] { return PowerPC::ppcState.spr[SPR_GQR0 + i]; }, nullptr);
} }
for (int i = 0; i < 16; i++) for (int i = 0; i < 16; i++)
@ -247,59 +250,71 @@ void RegisterWidget::PopulateTable()
} }
// Special registers // Special registers
// TB
AddRegister(16, 5, RegisterType::tb, "TB",
[] {
return static_cast<u64>(PowerPC::ppcState.spr[SPR_TU]) << 32 |
PowerPC::ppcState.spr[SPR_TL];
},
nullptr);
// PC // PC
AddRegister(16, 5, RegisterType::pc, "PC", [] { return PowerPC::ppcState.pc; }, AddRegister(17, 5, RegisterType::pc, "PC", [] { return PowerPC::ppcState.pc; },
[](u64 value) { PowerPC::ppcState.pc = value; }); [](u64 value) { PowerPC::ppcState.pc = value; });
// LR // LR
AddRegister(17, 5, RegisterType::fpscr, "LR", [] { return PowerPC::ppcState.spr[SPR_LR]; }, AddRegister(18, 5, RegisterType::lr, "LR", [] { return PowerPC::ppcState.spr[SPR_LR]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_LR] = value; }); [](u64 value) { PowerPC::ppcState.spr[SPR_LR] = value; });
// CTR // CTR
AddRegister(18, 5, RegisterType::fpscr, "FPSCR", [] { return PowerPC::ppcState.spr[SPR_CTR]; }, AddRegister(19, 5, RegisterType::ctr, "CTR", [] { return PowerPC::ppcState.spr[SPR_CTR]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_CTR] = value; }); [](u64 value) { PowerPC::ppcState.spr[SPR_CTR] = value; });
// CR // CR
AddRegister(19, 5, RegisterType::cr, "CR", [] { return GetCR(); }, AddRegister(20, 5, RegisterType::cr, "CR", [] { return GetCR(); },
[](u64 value) { SetCR(value); }); [](u64 value) { SetCR(value); });
// XER
AddRegister(21, 5, RegisterType::xer, "XER", [] { return GetXER().Hex; },
[](u64 value) { SetXER(UReg_XER(value)); });
// FPSCR // FPSCR
AddRegister(20, 5, RegisterType::fpscr, "FPSCR", [] { return PowerPC::ppcState.fpscr; }, AddRegister(22, 5, RegisterType::fpscr, "FPSCR", [] { return PowerPC::ppcState.fpscr; },
[](u64 value) { PowerPC::ppcState.fpscr = value; }); [](u64 value) { PowerPC::ppcState.fpscr = value; });
// MSR // MSR
AddRegister(21, 5, RegisterType::msr, "MSR", [] { return PowerPC::ppcState.msr; }, AddRegister(23, 5, RegisterType::msr, "MSR", [] { return PowerPC::ppcState.msr; },
[](u64 value) { PowerPC::ppcState.msr = value; }); [](u64 value) { PowerPC::ppcState.msr = value; });
// SRR 0-1 // SRR 0-1
AddRegister(22, 5, RegisterType::srr, "SRR0", [] { return PowerPC::ppcState.spr[SPR_SRR0]; }, AddRegister(24, 5, RegisterType::srr, "SRR0", [] { return PowerPC::ppcState.spr[SPR_SRR0]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_SRR0] = value; }); [](u64 value) { PowerPC::ppcState.spr[SPR_SRR0] = value; });
AddRegister(23, 5, RegisterType::srr, "SRR1", [] { return PowerPC::ppcState.spr[SPR_SRR1]; }, AddRegister(25, 5, RegisterType::srr, "SRR1", [] { return PowerPC::ppcState.spr[SPR_SRR1]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_SRR1] = value; }); [](u64 value) { PowerPC::ppcState.spr[SPR_SRR1] = value; });
// Exceptions // Exceptions
AddRegister(24, 5, RegisterType::exceptions, "Exceptions", AddRegister(26, 5, RegisterType::exceptions, "Exceptions",
[] { return PowerPC::ppcState.Exceptions; }, [] { return PowerPC::ppcState.Exceptions; },
[](u64 value) { PowerPC::ppcState.Exceptions = value; }); [](u64 value) { PowerPC::ppcState.Exceptions = value; });
// Int Mask // Int Mask
AddRegister(25, 5, RegisterType::int_mask, "Int Mask", AddRegister(27, 5, RegisterType::int_mask, "Int Mask",
[] { return ProcessorInterface::GetMask(); }, nullptr); [] { return ProcessorInterface::GetMask(); }, nullptr);
// Int Cause // Int Cause
AddRegister(26, 5, RegisterType::int_cause, "Int Cause", AddRegister(28, 5, RegisterType::int_cause, "Int Cause",
[] { return ProcessorInterface::GetCause(); }, nullptr); [] { return ProcessorInterface::GetCause(); }, nullptr);
// DSISR // DSISR
AddRegister(27, 5, RegisterType::dsisr, "DSISR", [] { return PowerPC::ppcState.spr[SPR_DSISR]; }, AddRegister(29, 5, RegisterType::dsisr, "DSISR", [] { return PowerPC::ppcState.spr[SPR_DSISR]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_DSISR] = value; }); [](u64 value) { PowerPC::ppcState.spr[SPR_DSISR] = value; });
// DAR // DAR
AddRegister(28, 5, RegisterType::dar, "DAR", [] { return PowerPC::ppcState.spr[SPR_DAR]; }, AddRegister(30, 5, RegisterType::dar, "DAR", [] { return PowerPC::ppcState.spr[SPR_DAR]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_DAR] = value; }); [](u64 value) { PowerPC::ppcState.spr[SPR_DAR] = value; });
// Hash Mask // Hash Mask
AddRegister( AddRegister(
29, 5, RegisterType::pt_hashmask, "Hash Mask", 31, 5, RegisterType::pt_hashmask, "Hash Mask",
[] { return (PowerPC::ppcState.pagetable_hashmask << 6) | PowerPC::ppcState.pagetable_base; }, [] { return (PowerPC::ppcState.pagetable_hashmask << 6) | PowerPC::ppcState.pagetable_base; },
nullptr); nullptr);