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Jit_FloatingPoint: fmrx

This commit is contained in:
MerryMage 2018-10-15 21:01:59 +01:00
parent fecbf091e5
commit 55c21a15a2
1 changed files with 11 additions and 12 deletions
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23
Source/Core/Core/PowerPC/Jit64/Jit_FloatingPoint.cpp
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@ -463,26 +463,25 @@ void Jit64::fmrx(UGeckoInstruction inst)
if (d == b) if (d == b)
return; return;
fpr.Lock(b, d); RCOpArg Rd = fpr.Use(d, RCMode::Write);
RegCache::Realize(Rd);
if (fpr.R(d).IsSimpleReg()) if (Rd.IsSimpleReg())
{ {
// We don't need to load d, but if it is loaded, we need to mark it as dirty. RCOpArg Rb = fpr.Use(b, RCMode::Read);
fpr.BindToRegister(d); RegCache::Realize(Rb);
// We have to use MOVLPD if b isn't loaded because "MOVSD reg, mem" sets the upper bits (64+) // We have to use MOVLPD if b isn't loaded because "MOVSD reg, mem" sets the upper bits (64+)
// to zero and we don't want that. // to zero and we don't want that.
if (!fpr.R(b).IsSimpleReg()) if (!Rb.IsSimpleReg())
MOVLPD(fpr.RX(d), fpr.R(b)); MOVLPD(Rd.GetSimpleReg(), Rb);
else else
MOVSD(fpr.R(d), fpr.RX(b)); MOVSD(Rd, Rb.GetSimpleReg());
} }
else else
{ {
fpr.BindToRegister(b, true, false); RCOpArg Rb = fpr.Bind(b, RCMode::Read);
MOVSD(fpr.R(d), fpr.RX(b)); RegCache::Realize(Rb);
MOVSD(Rd, Rb.GetSimpleReg());
} }
fpr.UnlockAll();
} }
void Jit64::FloatCompare(UGeckoInstruction inst, bool upper) void Jit64::FloatCompare(UGeckoInstruction inst, bool upper)