CR: Replace some magic values with constants.
This commit is contained in:
Pierre Bourdon
parent
0ff1481494
commit
5506e57ab8
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@ -237,33 +237,22 @@ void Jit64::fcmpx(UGeckoInstruction inst)
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pGreater = J_CC(CC_B);
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}
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// Read the documentation about cr_val in PowerPC.h to understand these
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// magic values.
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// Equal: !GT (bit 63 set), !LT (bit 62 not set), !SO (bit 61 not set), EQ
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// (bits 31-0 not set).
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MOV(64, R(RAX), Imm64(0x8000000000000000));
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MOV(64, R(RAX), Imm64(PPCCRToInternal(CR_EQ)));
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continue1 = J();
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// NAN: !GT (bit 63 set), !LT (bit 62 not set), SO (bit 61 set), !EQ (bit 0
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// set).
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SetJumpTarget(pNaN);
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MOV(64, R(RAX), Imm64(0xA000000000000001));
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MOV(64, R(RAX), Imm64(PPCCRToInternal(CR_SO)));
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if (a != b)
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{
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continue2 = J();
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// Greater Than: GT (bit 63 not set), !LT (bit 62 not set), !SO (bit 61
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// not set), !EQ (bit 0 set).
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SetJumpTarget(pGreater);
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MOV(64, R(RAX), Imm64(0x0000000000000001));
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MOV(64, R(RAX), Imm64(PPCCRToInternal(CR_GT)));
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continue3 = J();
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// Less Than: !GT (bit 63 set), LT (bit 62 set), !SO (bit 61 not set),
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// !EQ (bit 0 set).
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SetJumpTarget(pLesser);
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MOV(64, R(RAX), Imm64(0xC000000000000001));
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MOV(64, R(RAX), Imm64(PPCCRToInternal(CR_LT)));
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}
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SetJumpTarget(continue1);
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@ -315,20 +315,20 @@ void Jit64::cmpXX(UGeckoInstruction inst)
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if (signedCompare)
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{
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if ((s32)gpr.R(a).offset == (s32)comparand.offset)
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compareResult = 0x2;
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compareResult = CR_EQ;
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else if ((s32)gpr.R(a).offset > (s32)comparand.offset)
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compareResult = 0x4;
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compareResult = CR_GT;
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else
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compareResult = 0x8;
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compareResult = CR_LT;
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}
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else
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{
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if ((u32)gpr.R(a).offset == (u32)comparand.offset)
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compareResult = 0x2;
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compareResult = CR_EQ;
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else if ((u32)gpr.R(a).offset > (u32)comparand.offset)
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compareResult = 0x4;
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compareResult = CR_GT;
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else
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compareResult = 0x8;
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compareResult = CR_LT;
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}
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MOV(64, R(RAX), Imm64(PPCCRToInternal(compareResult)));
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MOV(64, M(&PowerPC::ppcState.cr_val[crf]), R(RAX));
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@ -14,24 +14,24 @@ void Jit64::GetCRFieldBit(int field, int bit, Gen::X64Reg out)
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{
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switch (bit)
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{
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case 0: // SO, check bit 61 set
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case CR_SO_BIT: // check bit 61 set
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 61));
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TEST(64, M(&PowerPC::ppcState.cr_val[field]), R(ABI_PARAM1));
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SETcc(CC_NZ, R(out));
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break;
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case 1: // EQ, check bits 31-0 == 0
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case CR_EQ_BIT: // check bits 31-0 == 0
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CMP(32, M(&PowerPC::ppcState.cr_val[field]), Imm32(0));
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SETcc(CC_Z, R(out));
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break;
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case 2: // GT, check val > 0
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case CR_GT_BIT: // check val > 0
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MOV(64, R(ABI_PARAM1), M(&PowerPC::ppcState.cr_val[field]));
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TEST(64, R(ABI_PARAM1), R(ABI_PARAM1));
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SETcc(CC_G, R(out));
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break;
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case 3: // LT, check bit 62 set
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case CR_LT_BIT: // check bit 62 set
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 62));
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TEST(64, M(&PowerPC::ppcState.cr_val[field]), R(ABI_PARAM1));
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SETcc(CC_NZ, R(out));
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@ -51,21 +51,21 @@ void Jit64::SetCRFieldBit(int field, int bit, Gen::X64Reg in)
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// New value is 0.
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switch (bit)
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{
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case 0: // !SO, unset bit 61
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case CR_SO_BIT: // unset bit 61
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MOV(64, R(ABI_PARAM1), Imm64(~(1ull << 61)));
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AND(64, R(ABI_PARAM2), R(ABI_PARAM1));
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break;
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case 1: // !EQ, set bit 0 to 1
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case CR_EQ_BIT: // set bit 0 to 1
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OR(8, R(ABI_PARAM2), Imm8(1));
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break;
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case 2: // !GT, set bit 63
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case CR_GT_BIT: // !GT, set bit 63
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 63));
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OR(64, R(ABI_PARAM2), R(ABI_PARAM1));
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break;
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case 3: // !LT, unset bit 62
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case CR_LT_BIT: // !LT, unset bit 62
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MOV(64, R(ABI_PARAM1), Imm64(~(1ull << 62)));
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AND(64, R(ABI_PARAM2), R(ABI_PARAM1));
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break;
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@ -76,22 +76,22 @@ void Jit64::SetCRFieldBit(int field, int bit, Gen::X64Reg in)
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switch (bit)
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{
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case 0: // SO, set bit 61
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case CR_SO_BIT: // set bit 61
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 61));
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OR(64, R(ABI_PARAM2), R(ABI_PARAM1));
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break;
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case 1: // EQ, set bits 31-0 to 0
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case CR_EQ_BIT: // set bits 31-0 to 0
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MOV(64, R(ABI_PARAM1), Imm64(0xFFFFFFFF00000000));
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AND(64, R(ABI_PARAM2), R(ABI_PARAM1));
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break;
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case 2: // GT, unset bit 63
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case CR_GT_BIT: // unset bit 63
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MOV(64, R(ABI_PARAM1), Imm64(~(1ull << 63)));
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AND(64, R(ABI_PARAM2), R(ABI_PARAM1));
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break;
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case 3: // LT, set bit 62
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case CR_LT_BIT: // set bit 62
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 62));
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OR(64, R(ABI_PARAM2), R(ABI_PARAM1));
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break;
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@ -107,21 +107,21 @@ FixupBranch Jit64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
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{
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switch (bit)
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{
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case 0: // SO, check bit 61 set
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case CR_SO_BIT: // check bit 61 set
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MOV(64, R(RAX), Imm64(1ull << 61));
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TEST(64, M(&PowerPC::ppcState.cr_val[field]), R(RAX));
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return J_CC(jump_if_set ? CC_NZ : CC_Z, true);
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case 1: // EQ, check bits 31-0 == 0
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case CR_EQ_BIT: // check bits 31-0 == 0
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CMP(32, M(&PowerPC::ppcState.cr_val[field]), Imm32(0));
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return J_CC(jump_if_set ? CC_Z : CC_NZ, true);
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case 2: // GT, check val > 0
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case CR_GT_BIT: // check val > 0
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MOV(64, R(RAX), M(&PowerPC::ppcState.cr_val[field]));
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TEST(64, R(RAX), R(RAX));
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return J_CC(jump_if_set ? CC_G : CC_LE, true);
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case 3: // LT, check bit 62 set
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case CR_LT_BIT: // check bit 62 set
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MOV(64, R(RAX), Imm64(1ull << 62));
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TEST(64, M(&PowerPC::ppcState.cr_val[field]), R(RAX));
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return J_CC(jump_if_set ? CC_NZ : CC_Z, true);
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@ -369,19 +369,19 @@ void Jit64::mtcrf(UGeckoInstruction inst)
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// EQ
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MOV(64, R(tmp), R(EAX));
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NOT(64, R(tmp));
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AND(64, R(tmp), Imm8(0x2));
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AND(64, R(tmp), Imm8(CR_EQ));
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OR(64, R(cr_val), R(tmp));
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// GT
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MOV(64, R(tmp), R(EAX));
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NOT(64, R(tmp));
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AND(64, R(tmp), Imm8(0x4));
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AND(64, R(tmp), Imm8(CR_GT));
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SHL(64, R(tmp), Imm8(63 - 2));
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OR(64, R(cr_val), R(tmp));
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// LT
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MOV(64, R(tmp), R(EAX));
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AND(64, R(tmp), Imm8(0x8));
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AND(64, R(tmp), Imm8(CR_LT));
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SHL(64, R(tmp), Imm8(62 - 3));
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OR(64, R(cr_val), R(tmp));
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@ -162,18 +162,27 @@ void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst);
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} // namespace
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enum CRBits
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{
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CR_SO = 1,
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CR_EQ = 2,
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CR_GT = 4,
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CR_LT = 8,
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CR_SO_BIT = 0,
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CR_EQ_BIT = 1,
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CR_GT_BIT = 2,
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CR_LT_BIT = 3,
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};
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// Convert between PPC and internal representation of CR.
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inline u64 PPCCRToInternal(u8 value)
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{
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u64 cr_val = 0x100000000;
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// SO
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cr_val |= (u64)!!(value & 1) << 61;
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// EQ
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cr_val |= (u64)!(value & 2);
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// GT
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cr_val |= (u64)!(value & 4) << 63;
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// LT
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cr_val |= (u64)!!(value & 8) << 62;
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cr_val |= (u64)!!(value & CR_SO) << 61;
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cr_val |= (u64)!(value & CR_EQ);
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cr_val |= (u64)!(value & CR_GT) << 63;
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cr_val |= (u64)!!(value & CR_LT) << 62;
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return cr_val;
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}
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