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Merge pull request #7631 from MerryMage/crXXX-AeqB 

Jit_SystemRegisters: Special-case crXXX for CRBA == CRBB
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Markus Wick 2018-12-23 17:55:09 +01:00 committed by GitHub
parent fc998093cc 174d2b0230
commit 54f37c3bae
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1 changed files with 31 additions and 14 deletions
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37
Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp
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@ -552,23 +552,40 @@ void Jit64::crXXX(UGeckoInstruction inst)
JITDISABLE(bJITSystemRegistersOff);
DEBUG_ASSERT_MSG(DYNA_REC, inst.OPCD == 19, "Invalid crXXX");
// Special case: crclr
if (inst.CRBA == inst.CRBB && inst.CRBA == inst.CRBD && inst.SUBOP10 == 193)
// TODO(merry): Futher optimizations can be performed here. For example,
// instead of extracting each CR field bit then setting it, the operation
// could be performed on the internal format directly instead and the
// relevant bit result can be masked out.
if (inst.CRBA == inst.CRBB)
{
switch (inst.SUBOP10)
{
// crclr
case 129: // crandc: A && ~B => 0
case 193: // crxor: A ^ B => 0
ClearCRFieldBit(inst.CRBD >> 2, 3 - (inst.CRBD & 3));
return;
}
// Special case: crset
if (inst.CRBA == inst.CRBB && inst.CRBA == inst.CRBD && inst.SUBOP10 == 289)
{
// crset
case 289: // creqv: ~(A ^ B) => 1
case 417: // crorc: A || ~B => 1
SetCRFieldBit(inst.CRBD >> 2, 3 - (inst.CRBD & 3));
return;
}
// TODO(delroth): Potential optimizations could be applied here. For
// instance, if the two CR bits being loaded are the same, two loads are
// not required.
case 257: // crand: A && B => A
case 449: // cror: A || B => A
GetCRFieldBit(inst.CRBA >> 2, 3 - (inst.CRBA & 3), RSCRATCH, false);
SetCRFieldBit(inst.CRBD >> 2, 3 - (inst.CRBD & 3), RSCRATCH);
return;
case 33: // crnor: ~(A || B) => ~A
case 225: // crnand: ~(A && B) => ~A
GetCRFieldBit(inst.CRBA >> 2, 3 - (inst.CRBA & 3), RSCRATCH, true);
SetCRFieldBit(inst.CRBD >> 2, 3 - (inst.CRBD & 3), RSCRATCH);
return;
}
}
// creqv or crnand or crnor
bool negateA = inst.SUBOP10 == 289 || inst.SUBOP10 == 225 || inst.SUBOP10 == 33;