x64Emitter: short MOV for 64bit immediates (2)
Prior to this commit, the emitter would unconditionally emit a 10-byte instruction known as MOVABS when loading a 64-bit immediate to a register. 0: 48 b8 ef be ad de 00 movabs rax,0xdeadbeef 7: 00 00 00 With this change, it will instead rely on the fact that on x64 writes to 32-bit registers are automatically zero extended to 64-bits, allowing us to emit a 5 or 6-bytes instruction with the same effect for certain immediates. 0: b8 ef be ad de mov eax,0xdeadbeef
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@ -1591,6 +1591,12 @@ void XEmitter::XOR(int bits, const OpArg& a1, const OpArg& a2)
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}
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}
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void XEmitter::MOV(int bits, const OpArg& a1, const OpArg& a2)
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void XEmitter::MOV(int bits, const OpArg& a1, const OpArg& a2)
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{
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{
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if (bits == 64 && a1.IsSimpleReg() && a2.scale == SCALE_IMM64 &&
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a2.offset == static_cast<u32>(a2.offset))
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{
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WriteNormalOp(32, NormalOp::MOV, a1, a2.AsImm32());
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return;
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}
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if (a1.IsSimpleReg() && a2.IsSimpleReg() && a1.GetSimpleReg() == a2.GetSimpleReg())
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if (a1.IsSimpleReg() && a2.IsSimpleReg() && a1.GetSimpleReg() == a2.GetSimpleReg())
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ERROR_LOG(DYNA_REC, "Redundant MOV @ %p - bug in JIT?", code);
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ERROR_LOG(DYNA_REC, "Redundant MOV @ %p - bug in JIT?", code);
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WriteNormalOp(bits, NormalOp::MOV, a1, a2);
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WriteNormalOp(bits, NormalOp::MOV, a1, a2);
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