Merge pull request #6513 from lioncash/dead-code
Interpreter: Remove dead code
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commit
5369d3c9f1
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@ -137,18 +137,6 @@ void Interpreter::oris(UGeckoInstruction inst)
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void Interpreter::subfic(UGeckoInstruction inst)
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{
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/* u32 rra = ~rGPR[inst.RA];
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s32 immediate = (s16)inst.SIMM_16 + 1;
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// #define CALC_XER_CA(X,Y) (((X) + (Y) < X) ? SET_XER_CA : CLEAR_XER_CA)
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if ((rra + immediate) < rra)
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PowerPC::SetCarry(1);
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else
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PowerPC::SetCarry(0);
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rGPR[inst.RD] = rra - immediate;
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*/
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s32 immediate = inst.SIMM_16;
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rGPR[inst.RD] = immediate - (int)rGPR[inst.RA];
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PowerPC::SetCarry((rGPR[inst.RA] == 0) || (Helper_Carry(0 - rGPR[inst.RA], immediate)));
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@ -621,7 +621,6 @@ void Interpreter::sthx(UGeckoInstruction inst)
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PowerPC::Write_U16((u16)rGPR[inst.RS], Helper_Get_EA_X(inst));
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}
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// __________________________________________________________________________________________________
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// lswi - bizarro string instruction
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// FIXME: Should rollback if a DSI occurs
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void Interpreter::lswi(UGeckoInstruction inst)
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@ -667,7 +666,6 @@ void Interpreter::lswi(UGeckoInstruction inst)
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}
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// todo : optimize ?
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// __________________________________________________________________________________________________
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// stswi - bizarro string instruction
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// FIXME: Should rollback if a DSI occurs
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void Interpreter::stswi(UGeckoInstruction inst)
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@ -804,5 +802,5 @@ void Interpreter::tlbie(UGeckoInstruction inst)
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void Interpreter::tlbsync(UGeckoInstruction inst)
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{
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// MessageBox(0,"TLBsync","TLBsyncE",0);
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// Ignored
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}
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@ -49,9 +49,6 @@ void Interpreter::mtfsb0x(UGeckoInstruction inst)
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{
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u32 b = 0x80000000 >> inst.CRBD;
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/*if (b & 0x9ff80700)
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PanicAlert("mtfsb0 clears bit %d, PC=%x", inst.CRBD, PC);*/
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FPSCR.Hex &= ~b;
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FPSCRtoFPUSettings(FPSCR);
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@ -78,10 +75,6 @@ void Interpreter::mtfsfix(UGeckoInstruction inst)
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u32 mask = (0xF0000000 >> (4 * inst.CRFD));
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u32 imm = (inst.hex << 16) & 0xF0000000;
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/*u32 cleared = ~(imm >> (4 * _inst.CRFD)) & FPSCR.Hex & mask;
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if (cleared & 0x9ff80700)
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PanicAlert("mtfsfi clears %08x, PC=%x", cleared, PC);*/
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FPSCR.Hex = (FPSCR.Hex & ~mask) | (imm >> (4 * inst.CRFD));
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FPSCRtoFPUSettings(FPSCR);
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@ -100,10 +93,6 @@ void Interpreter::mtfsfx(UGeckoInstruction inst)
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m |= (0xF << (i * 4));
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}
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/*u32 cleared = ~((u32)(riPS0(_inst.FB))) & FPSCR.Hex & m;
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if (cleared & 0x9ff80700)
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PanicAlert("mtfsf clears %08x, PC=%x", cleared, PC);*/
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FPSCR.Hex = (FPSCR.Hex & ~m) | ((u32)(riPS0(inst.FB)) & m);
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FPSCRtoFPUSettings(FPSCR);
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@ -336,8 +325,7 @@ void Interpreter::mtspr(UGeckoInstruction inst)
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u32 dwMemAddress = DMAU.MEM_ADDR << 5;
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u32 dwCacheAddress = DMAL.LC_ADDR << 5;
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u32 iLength = ((DMAU.DMA_LEN_U << 2) | DMAL.DMA_LEN_L);
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// INFO_LOG(POWERPC, "DMA: mem = %x, cache = %x, len = %u, LD = %d, PC=%x", dwMemAddress,
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// dwCacheAddress, iLength, (int)DMAL.DMA_LD, PC);
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if (iLength == 0)
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iLength = 128;
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if (DMAL.DMA_LD)
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@ -349,7 +337,6 @@ void Interpreter::mtspr(UGeckoInstruction inst)
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break;
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case SPR_L2CR:
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// PanicAlert("mtspr( L2CR )!");
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break;
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case SPR_DEC:
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@ -473,9 +460,6 @@ void Interpreter::isync(UGeckoInstruction inst)
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void Interpreter::mcrfs(UGeckoInstruction inst)
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{
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// if (_inst.CRFS != 3 && _inst.CRFS != 4)
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// PanicAlert("msrfs at %x, CRFS = %d, CRFD = %d", PC, (int)_inst.CRFS, (int)_inst.CRFD);
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UpdateFPSCR();
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u32 fpflags = ((FPSCR.Hex >> (4 * (7 - inst.CRFS))) & 0xF);
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switch (inst.CRFS)
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@ -561,8 +561,6 @@ void CheckBreakPoints()
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void UpdateFPRF(double dvalue)
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{
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FPSCR.FPRF = MathUtil::ClassifyDouble(dvalue);
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// if (FPSCR.FPRF == 0x11)
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// PanicAlert("QNAN alert");
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}
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} // namespace PowerPC
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