comments, tstaxl guessing, clear log messages
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2914 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -386,7 +386,11 @@ void ilrrn(const UDSPInstruction& opc)
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g_dsp.r[reg] += g_dsp.r[DSP_REG_IX0 + reg];
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}
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// LRI $D, #I
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// 0000 0000 100d dddd
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// iiii iiii iiii iiii
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// Load immediate value I to register $D.
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// FIXME: Perform additional operation depending on destination register.
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void lri(const UDSPInstruction& opc)
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{
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u8 reg = opc.hex & DSP_REG_MASK;
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@ -394,6 +398,10 @@ void lri(const UDSPInstruction& opc)
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dsp_op_write_reg(reg, imm);
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}
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// LRIS $(0x18+D), #I
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// 0000 1ddd iiii iiii
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// Load immediate value I (8-bit sign extended) to accumulator register$(0x18+D).
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// FIXME: Perform additional operation depending on destination register.
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void lris(const UDSPInstruction& opc)
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{
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u8 reg = ((opc.hex >> 8) & 0x7) + 0x18;
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@ -401,6 +409,11 @@ void lris(const UDSPInstruction& opc)
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dsp_op_write_reg(reg, imm);
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}
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// LR $D, @M
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// 0000 0000 110d dddd
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// mmmm mmmm mmmm mmmm
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// Move value from data memory pointed by address M to register $D.
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// FIXME: Perform additional operation depending on destination register.
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void lr(const UDSPInstruction& opc)
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{
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u8 reg = opc.hex & DSP_REG_MASK;
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@ -409,6 +422,11 @@ void lr(const UDSPInstruction& opc)
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dsp_op_write_reg(reg, val);
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}
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// SR @M, $S
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// 0000 0000 111s ssss
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// mmmm mmmm mmmm mmmm
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// Store value from register $S to a memory pointed by address M.
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// FIXME: Perform additional operation depending on destination register.
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void sr(const UDSPInstruction& opc)
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{
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u8 reg = opc.hex & DSP_REG_MASK;
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@ -417,6 +435,11 @@ void sr(const UDSPInstruction& opc)
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dsp_dmem_write(addr, val);
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}
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// SI @M, #I
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// 0001 0110 mmmm mmmm
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// iiii iiii iiii iiii
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// Store 16-bit immediate value I to a memory location pointed by address
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// M (M is 8-bit value sign extended).
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void si(const UDSPInstruction& opc)
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{
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u16 addr = (s8)opc.hex;
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@ -424,6 +447,9 @@ void si(const UDSPInstruction& opc)
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dsp_dmem_write(addr, imm);
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}
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// TSTAXH $axR.h
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// 1000 011r xxxx xxxx
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// Test hight part of secondary accumulator $axR.h.
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void tstaxh(const UDSPInstruction& opc)
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{
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u8 reg = (opc.hex >> 8) & 0x1;
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@ -432,6 +458,17 @@ void tstaxh(const UDSPInstruction& opc)
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Update_SR_Register16(val);
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}
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// TSTAXL $axR.h
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// 1000 011r xxxx xxxx
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// Test lower part of secondary accumulator $axR.h.
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void tstaxl(const UDSPInstruction& opc)
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{
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u8 reg = (opc.hex >> 8) & 0x1;
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s16 val = dsp_get_ax_l(reg);
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Update_SR_Register16(val);
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}
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// CLR $acR
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// 1000 r001 xxxx xxxx
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// Clears accumulator $acR
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@ -1222,33 +1259,33 @@ void srbith(const UDSPInstruction& opc)
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// done around loops with lots of multiplications.
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case 0xa: // M2
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ERROR_LOG(DSPLLE, "M2");
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//ERROR_LOG(DSPLLE, "M2");
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break;
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// FIXME: Both of these appear in the beginning of the Wind Waker
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case 0xb: // M0
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ERROR_LOG(DSPLLE, "M0");
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//ERROR_LOG(DSPLLE, "M0");
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break;
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// 15-bit precision? clamping? no idea :(
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// CLR15 seems to be the default.
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case 0xc: // CLR15
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ERROR_LOG(DSPLLE, "CLR15");
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//ERROR_LOG(DSPLLE, "CLR15");
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break;
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case 0xd: // SET15
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ERROR_LOG(DSPLLE, "SET15");
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//ERROR_LOG(DSPLLE, "SET15");
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break;
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// 40-bit precision? clamping? no idea :(
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// 40 seems to be the default.
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case 0xe: // SET40 (really, clear SR's 0x4000?) something about "set 40-bit operation"?
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g_dsp.r[DSP_REG_SR] &= ~(1 << 14);
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ERROR_LOG(DSPLLE, "SET40");
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//ERROR_LOG(DSPLLE, "SET40");
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break;
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case 0xf: // SET16 (really, set SR's 0x4000?) something about "set 16-bit operation"?
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// that doesnt happen on a real console << what does this comment mean?
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g_dsp.r[DSP_REG_SR] |= (1 << 14);
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ERROR_LOG(DSPLLE, "SET16");
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//ERROR_LOG(DSPLLE, "SET16");
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break;
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default:
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@ -136,7 +136,7 @@ void srbith(const UDSPInstruction& opc);
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// END OF FIXMEs
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// TODO: PENDING IMPLEMENTATION / UNIMPLEMENTED
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void tstaxl(const UDSPInstruction& opc);
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// The mysterious a100
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// END OF UNIMPLEMENTED
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@ -232,6 +232,9 @@ DSPOPCTemplate opcodes[] =
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{"TST", 0xb100, 0xf7ff, DSPInterpreter::tst, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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// GUESSING NOT SURE AT ALL!!!!
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{"TSTAXL", 0xa100, 0xfeff, DSPInterpreter::tstaxl, nop, 1 | P_EXT, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"TSTAXH", 0x8600, 0xfeff, DSPInterpreter::tstaxh, nop, 1 | P_EXT, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"CMP", 0x8200, 0xffff, DSPInterpreter::cmp, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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@ -266,7 +269,6 @@ DSPOPCTemplate opcodes[] =
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{"ORC", 0x3E00, 0xfeff, nop, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // Hermes doesn't list this
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{"MULX", 0xa000, 0xe7ff, DSPInterpreter::mulx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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// {"MULX???", 0xa100, 0xf7ff, DSPInterpreter::unknown,nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"MULXMVZ", 0xa200, 0xe6ff, DSPInterpreter::mulxmvz, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"MULXAC", 0xa400, 0xe6ff, DSPInterpreter::mulxac, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"MULXMV", 0xa600, 0xe6ff, DSPInterpreter::mulxmv, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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@ -120,7 +120,7 @@ bool CheckCondition(u8 _Condition)
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break;
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case 0x6: // L - LESS
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if ((g_dsp.r[DSP_REG_SR] & 0x02) || (g_dsp.r[DSP_REG_SR] & 0x08))
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if (!(g_dsp.r[DSP_REG_SR] & 0x02) && (g_dsp.r[DSP_REG_SR] & 0x08))
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taken = true;
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break;
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