From 52f9912c46345b21b20be0795a471a744389d305 Mon Sep 17 00:00:00 2001
From: degasus <wickmarkus@web.de>
Date: Wed, 10 Feb 2016 16:00:20 +0100
Subject: [PATCH] ArmJit64: Merge FP two operant instructions.

---
 Source/Core/Core/PowerPC/JitArm64/Jit.h       |  5 +-
 .../JitArm64/JitArm64_FloatingPoint.cpp       | 54 ++++---------------
 .../Core/PowerPC/JitArm64/JitArm64_Tables.cpp |  8 +--
 3 files changed, 16 insertions(+), 51 deletions(-)

diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.h b/Source/Core/Core/PowerPC/JitArm64/Jit.h
index cdff0ebdde..7bd62b0aab 100644
--- a/Source/Core/Core/PowerPC/JitArm64/Jit.h
+++ b/Source/Core/Core/PowerPC/JitArm64/Jit.h
@@ -138,10 +138,7 @@ public:
 
 	// Floating point
 	void fp_arith(UGeckoInstruction inst);
-	void fabsx(UGeckoInstruction inst);
-	void fmrx(UGeckoInstruction inst);
-	void fnabsx(UGeckoInstruction inst);
-	void fnegx(UGeckoInstruction inst);
+	void fp_logic(UGeckoInstruction inst);
 	void fselx(UGeckoInstruction inst);
 	void fcmpX(UGeckoInstruction inst);
 	void frspx(UGeckoInstruction inst);
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
index 52af9af6a6..9d96ed70c9 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
@@ -17,19 +17,6 @@
 
 using namespace Arm64Gen;
 
-void JitArm64::fabsx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 b = inst.FB, d = inst.FD;
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
-
-	m_float_emit.FABS(EncodeRegToDouble(VD), EncodeRegToDouble(VB));
-}
-
 void JitArm64::fp_arith(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
@@ -93,7 +80,7 @@ void JitArm64::fp_arith(UGeckoInstruction inst)
 		fpr.FixSinglePrecision(d);
 }
 
-void JitArm64::fmrx(UGeckoInstruction inst)
+void JitArm64::fp_logic(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(bJITFloatingPointOff);
@@ -101,39 +88,20 @@ void JitArm64::fmrx(UGeckoInstruction inst)
 
 	u32 b = inst.FB, d = inst.FD;
 
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
-
-	m_float_emit.INS(64, VD, 0, VB, 0);
-}
-
-void JitArm64::fnabsx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 b = inst.FB, d = inst.FD;
+	u32 op10 = inst.SUBOP10;
 
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
 	ARM64Reg VD = fpr.RW(d);
 
-	m_float_emit.FABS(EncodeRegToDouble(VD), EncodeRegToDouble(VB));
-	m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VD));
-}
-
-void JitArm64::fnegx(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITFloatingPointOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 b = inst.FB, d = inst.FD;
-
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
-
-	m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VB));
+	switch (op10)
+	{
+	case  40: m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VB)); break;
+	case  72: m_float_emit.INS(64, VD, 0, VB, 0); break;
+	case 136: m_float_emit.FABS(EncodeRegToDouble(VD), EncodeRegToDouble(VB));
+	          m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VD)); break;
+	case 264: m_float_emit.FABS(EncodeRegToDouble(VD), EncodeRegToDouble(VB)); break;
+	default: _assert_msg_(DYNA_REC, 0, "fp_logic WTF!!!");
+	}
 }
 
 void JitArm64::fselx(UGeckoInstruction inst)
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
index f704ffd0c2..7a109ff14a 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
@@ -326,14 +326,14 @@ static GekkoOPTemplate table59[] =
 
 static GekkoOPTemplate table63[] =
 {
-	{264, &JitArm64::fabsx},                    // fabsx
+	{264, &JitArm64::fp_logic},                 // fabsx
 	{32,  &JitArm64::fcmpX},                    // fcmpo
 	{0,   &JitArm64::fcmpX},                    // fcmpu
 	{14,  &JitArm64::FallBackToInterpreter},    // fctiwx
 	{15,  &JitArm64::fctiwzx},                  // fctiwzx
-	{72,  &JitArm64::fmrx},                     // fmrx
-	{136, &JitArm64::fnabsx},                   // fnabsx
-	{40,  &JitArm64::fnegx},                    // fnegx
+	{72,  &JitArm64::fp_logic},                 // fmrx
+	{136, &JitArm64::fp_logic},                 // fnabsx
+	{40,  &JitArm64::fp_logic},                 // fnegx
 	{12,  &JitArm64::frspx},                    // frspx
 
 	{64,  &JitArm64::FallBackToInterpreter},    // mcrfs