Merge pull request #4188 from degasus/dynamic-bat
Dynamic bat: Merge failure and small cleanup
This commit is contained in:
commit
5045fc869c
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@ -34,9 +34,6 @@
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namespace Memory
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{
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// (See comment below describing memory map.)
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bool bFakeVMEM = false;
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// =================================
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// Init() declarations
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// ----------------
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@ -169,6 +166,7 @@ void Init()
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{
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bool wii = SConfig::GetInstance().bWii;
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bool bMMU = SConfig::GetInstance().bMMU;
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bool bFakeVMEM = false;
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#ifndef _ARCH_32
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// If MMU is turned off in GameCube mode, turn on fake VMEM hack.
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// The fake VMEM hack's address space is above the memory space that we
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@ -269,7 +267,7 @@ void DoState(PointerWrap& p)
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p.DoArray(m_pRAM, RAM_SIZE);
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p.DoArray(m_pL1Cache, L1_CACHE_SIZE);
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p.DoMarker("Memory RAM");
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if (bFakeVMEM)
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if (m_pFakeVMEM)
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p.DoArray(m_pFakeVMEM, FAKEVMEM_SIZE);
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p.DoMarker("Memory FakeVMEM");
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if (wii)
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@ -283,7 +281,7 @@ void Shutdown()
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u32 flags = 0;
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if (SConfig::GetInstance().bWii)
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flags |= PhysicalMemoryRegion::WII_ONLY;
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if (bFakeVMEM)
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if (m_pFakeVMEM)
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flags |= PhysicalMemoryRegion::FAKE_VMEM;
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for (PhysicalMemoryRegion& region : physical_regions)
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{
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@ -397,7 +395,7 @@ u8* GetPointer(u32 address)
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if (address < REALRAM_SIZE)
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return m_pRAM + address;
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if (SConfig::GetInstance().bWii)
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if (m_pEXRAM)
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{
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if ((address >> 28) == 0x1 && (address & 0x0fffffff) < EXRAM_SIZE)
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return m_pEXRAM + (address & EXRAM_MASK);
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@ -35,7 +35,6 @@ extern u8* m_pRAM;
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extern u8* m_pEXRAM;
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extern u8* m_pL1Cache;
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extern u8* m_pFakeVMEM;
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extern bool bFakeVMEM;
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enum
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{
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@ -373,7 +373,7 @@ void Jit64::dcbz(UGeckoInstruction inst)
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MOV(32, M(&PC), Imm32(jit->js.compilerPC));
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BitSet32 registersInUse = CallerSavedRegistersInUse();
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ABI_PushRegistersAndAdjustStack(registersInUse, 0);
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ABI_CallFunctionR(&PowerPC::ClearCacheLine, RSCRATCH);
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ABI_CallFunctionR(PowerPC::ClearCacheLine, RSCRATCH);
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ABI_PopRegistersAndAdjustStack(registersInUse, 0);
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if (UReg_MSR(MSR).DR)
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@ -163,7 +163,7 @@ BatTable dbat_table;
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static void GenerateDSIException(u32 _EffectiveAddress, bool _bWrite);
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template <XCheckTLBFlag flag, typename T, bool never_translate = false>
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__forceinline static T ReadFromHardware(u32 em_address)
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static T ReadFromHardware(u32 em_address)
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{
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if (!never_translate && UReg_MSR(MSR).DR)
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{
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@ -203,27 +203,6 @@ __forceinline static T ReadFromHardware(u32 em_address)
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// TODO: Make sure these are safe for unaligned addresses.
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// Locked L1 technically doesn't have a fixed address, but games all use 0xE0000000.
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if ((em_address >> 28) == 0xE && (em_address < (0xE0000000 + Memory::L1_CACHE_SIZE)))
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{
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return bswap((*(const T*)&Memory::m_pL1Cache[em_address & 0x0FFFFFFF]));
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}
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// In Fake-VMEM mode, we need to map the memory somewhere into
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// physical memory for BAT translation to work; we currently use
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// [0x7E000000, 0x80000000).
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if (Memory::bFakeVMEM && ((em_address & 0xFE000000) == 0x7E000000))
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{
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return bswap(*(T*)&Memory::m_pFakeVMEM[em_address & Memory::RAM_MASK]);
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}
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if (flag == FLAG_READ && (em_address & 0xF8000000) == 0x08000000)
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{
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if (em_address < 0x0c000000)
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return EFB_Read(em_address);
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else
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return (T)Memory::mmio_mapping->Read<typename std::make_unsigned<T>::type>(em_address);
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}
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if ((em_address & 0xF8000000) == 0x00000000)
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{
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// Handle RAM; the masking intentionally discards bits (essentially creating
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@ -238,12 +217,33 @@ __forceinline static T ReadFromHardware(u32 em_address)
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return bswap((*(const T*)&Memory::m_pEXRAM[em_address & 0x0FFFFFFF]));
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}
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// Locked L1 technically doesn't have a fixed address, but games all use 0xE0000000.
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if ((em_address >> 28) == 0xE && (em_address < (0xE0000000 + Memory::L1_CACHE_SIZE)))
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{
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return bswap((*(const T*)&Memory::m_pL1Cache[em_address & 0x0FFFFFFF]));
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}
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// In Fake-VMEM mode, we need to map the memory somewhere into
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// physical memory for BAT translation to work; we currently use
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// [0x7E000000, 0x80000000).
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if (Memory::m_pFakeVMEM && ((em_address & 0xFE000000) == 0x7E000000))
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{
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return bswap(*(T*)&Memory::m_pFakeVMEM[em_address & Memory::RAM_MASK]);
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}
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if (flag == FLAG_READ && (em_address & 0xF8000000) == 0x08000000)
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{
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if (em_address < 0x0c000000)
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return EFB_Read(em_address);
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else
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return (T)Memory::mmio_mapping->Read<typename std::make_unsigned<T>::type>(em_address);
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}
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PanicAlert("Unable to resolve read address %x PC %x", em_address, PC);
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return 0;
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}
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template <XCheckTLBFlag flag, typename T, bool never_translate = false>
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__forceinline static void WriteToHardware(u32 em_address, const T data)
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static void WriteToHardware(u32 em_address, const T data)
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{
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if (!never_translate && UReg_MSR(MSR).DR)
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{
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@ -285,6 +285,22 @@ __forceinline static void WriteToHardware(u32 em_address, const T data)
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// TODO: Make sure these are safe for unaligned addresses.
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if ((em_address & 0xF8000000) == 0x00000000)
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{
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// Handle RAM; the masking intentionally discards bits (essentially creating
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// mirrors of memory).
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// TODO: Only the first REALRAM_SIZE is supposed to be backed by actual memory.
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*(T*)&Memory::m_pRAM[em_address & Memory::RAM_MASK] = bswap(data);
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return;
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}
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if (Memory::m_pEXRAM && (em_address >> 28) == 0x1 &&
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(em_address & 0x0FFFFFFF) < Memory::EXRAM_SIZE)
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{
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*(T*)&Memory::m_pEXRAM[em_address & 0x0FFFFFFF] = bswap(data);
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return;
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}
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// Locked L1 technically doesn't have a fixed address, but games all use 0xE0000000.
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if ((em_address >> 28 == 0xE) && (em_address < (0xE0000000 + Memory::L1_CACHE_SIZE)))
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{
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@ -295,7 +311,7 @@ __forceinline static void WriteToHardware(u32 em_address, const T data)
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// In Fake-VMEM mode, we need to map the memory somewhere into
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// physical memory for BAT translation to work; we currently use
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// [0x7E000000, 0x80000000).
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if (Memory::bFakeVMEM && ((em_address & 0xFE000000) == 0x7E000000))
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if (Memory::m_pFakeVMEM && ((em_address & 0xFE000000) == 0x7E000000))
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{
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*(T*)&Memory::m_pFakeVMEM[em_address & Memory::RAM_MASK] = bswap(data);
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return;
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@ -337,22 +353,6 @@ __forceinline static void WriteToHardware(u32 em_address, const T data)
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}
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}
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if ((em_address & 0xF8000000) == 0x00000000)
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{
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// Handle RAM; the masking intentionally discards bits (essentially creating
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// mirrors of memory).
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// TODO: Only the first REALRAM_SIZE is supposed to be backed by actual memory.
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*(T*)&Memory::m_pRAM[em_address & Memory::RAM_MASK] = bswap(data);
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return;
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}
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if (Memory::m_pEXRAM && (em_address >> 28) == 0x1 &&
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(em_address & 0x0FFFFFFF) < Memory::EXRAM_SIZE)
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{
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*(T*)&Memory::m_pEXRAM[em_address & 0x0FFFFFFF] = bswap(data);
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return;
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}
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PanicAlert("Unable to resolve write address %x PC %x", em_address, PC);
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return;
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}
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@ -395,7 +395,7 @@ TryReadInstResult TryReadInstruction(u32 address)
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u32 hex;
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// TODO: Refactor this. This icache implementation is totally wrong if used with the fake vmem.
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if (Memory::bFakeVMEM && ((address & 0xFE000000) == 0x7E000000))
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if (Memory::m_pFakeVMEM && ((address & 0xFE000000) == 0x7E000000))
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{
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hex = bswap(*(const u32*)&Memory::m_pFakeVMEM[address & Memory::FAKEVMEM_MASK]);
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}
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@ -412,7 +412,7 @@ u32 HostRead_Instruction(const u32 address)
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return inst.hex;
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}
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static __forceinline void Memcheck(u32 address, u32 var, bool write, int size)
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static void Memcheck(u32 address, u32 var, bool write, int size)
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{
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if (PowerPC::memchecks.HasAny())
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{
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@ -639,7 +639,7 @@ bool HostIsRAMAddress(u32 address)
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return true;
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else if (Memory::m_pEXRAM && segment == 0x1 && (address & 0x0FFFFFFF) < Memory::EXRAM_SIZE)
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return true;
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else if (Memory::bFakeVMEM && ((address & 0xFE000000) == 0x7E000000))
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else if (Memory::m_pFakeVMEM && ((address & 0xFE000000) == 0x7E000000))
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return true;
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else if (segment == 0xE && (address < (0xE0000000 + Memory::L1_CACHE_SIZE)))
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return true;
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@ -953,8 +953,7 @@ enum TLBLookupResult
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TLB_UPDATE_C
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};
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static __forceinline TLBLookupResult LookupTLBPageAddress(const XCheckTLBFlag flag, const u32 vpa,
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u32* paddr)
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static TLBLookupResult LookupTLBPageAddress(const XCheckTLBFlag flag, const u32 vpa, u32* paddr)
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{
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u32 tag = vpa >> HW_PAGE_INDEX_SHIFT;
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PowerPC::tlb_entry* tlbe = &PowerPC::ppcState.tlb[IsOpcodeFlag(flag)][tag & HW_PAGE_INDEX_MASK];
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@ -1005,7 +1004,7 @@ static __forceinline TLBLookupResult LookupTLBPageAddress(const XCheckTLBFlag fl
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return TLB_NOTFOUND;
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}
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static __forceinline void UpdateTLBEntry(const XCheckTLBFlag flag, UPTE2 PTE2, const u32 address)
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static void UpdateTLBEntry(const XCheckTLBFlag flag, UPTE2 PTE2, const u32 address)
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{
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if (IsNoExceptionFlag(flag))
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return;
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@ -1032,8 +1031,7 @@ void InvalidateTLBEntry(u32 address)
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}
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// Page Address Translation
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static __forceinline TranslateAddressResult TranslatePageAddress(const u32 address,
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const XCheckTLBFlag flag)
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static TranslateAddressResult TranslatePageAddress(const u32 address, const XCheckTLBFlag flag)
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{
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// TLB cache
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// This catches 99%+ of lookups in practice, so the actual page table entry code below doesn't
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@ -1166,7 +1164,7 @@ static void UpdateBATs(BatTable& bat_table, u32 base_spr)
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// The bottom bit is whether the translation is valid; the second
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// bit from the bottom is whether we can use the fastmem arena.
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u32 valid_bit = 0x1;
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if (Memory::bFakeVMEM && ((address & 0xFE000000) == 0x7E000000))
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if (Memory::m_pFakeVMEM && ((address & 0xFE000000) == 0x7E000000))
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valid_bit = 0x3;
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else if (address < Memory::REALRAM_SIZE)
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valid_bit = 0x3;
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@ -1202,13 +1200,16 @@ void DBATUpdated()
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bool extended_bats = SConfig::GetInstance().bWii && HID4.SBE;
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if (extended_bats)
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UpdateBATs(dbat_table, SPR_DBAT4U);
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if (Memory::bFakeVMEM)
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if (Memory::m_pFakeVMEM)
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{
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// In Fake-MMU mode, insert some extra entries into the BAT tables.
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UpdateFakeMMUBat(dbat_table, 0x40000000);
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UpdateFakeMMUBat(dbat_table, 0x70000000);
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}
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#ifndef _ARCH_32
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Memory::UpdateLogicalMemory(dbat_table);
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#endif
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// IsOptimizable*Address and dcbz depends on the BAT mapping, so we need a flush here.
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JitInterface::ClearSafe();
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@ -1221,7 +1222,7 @@ void IBATUpdated()
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bool extended_bats = SConfig::GetInstance().bWii && HID4.SBE;
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if (extended_bats)
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UpdateBATs(ibat_table, SPR_IBAT4U);
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if (Memory::bFakeVMEM)
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if (Memory::m_pFakeVMEM)
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{
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// In Fake-MMU mode, insert some extra entries into the BAT tables.
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UpdateFakeMMUBat(ibat_table, 0x40000000);
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@ -1235,7 +1236,7 @@ void IBATUpdated()
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// So we first check if there is a matching BAT entry, else we look for the TLB in
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// TranslatePageAddress().
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template <const XCheckTLBFlag flag>
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TranslateAddressResult TranslateAddress(const u32 address)
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static TranslateAddressResult TranslateAddress(const u32 address)
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{
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u32 bat_result = (flag == FLAG_OPCODE ? ibat_table : dbat_table)[address >> BAT_INDEX_SHIFT];
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if (bat_result & 1)
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