commit
4fb90bf9f6
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@ -3,6 +3,10 @@
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <array>
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#include "Common/CommonFuncs.h"
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#include "Common/CommonTypes.h"
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#include "Common/Event.h"
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#include "Common/FileUtil.h"
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@ -33,7 +37,9 @@ static bool VerifyRoms()
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{
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u32 hash_irom; // dsp_rom.bin
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u32 hash_drom; // dsp_coef.bin
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} KNOWN_ROMS[] = {
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};
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static const std::array<DspRomHashes, 4> known_roms = {{
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// Official Nintendo ROM
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{ 0x66f334fe, 0xf3b93527 },
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@ -46,17 +52,17 @@ static bool VerifyRoms()
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// above with improved resampling coefficients
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{ 0xd9907f71, 0xdb6880c1 }
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};
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}};
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u32 hash_irom = HashAdler32((u8*)g_dsp.irom, DSP_IROM_BYTE_SIZE);
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u32 hash_drom = HashAdler32((u8*)g_dsp.coef, DSP_COEF_BYTE_SIZE);
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int rom_idx = -1;
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for (u32 i = 0; i < sizeof (KNOWN_ROMS) / sizeof (KNOWN_ROMS[0]); ++i)
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for (size_t i = 0; i < known_roms.size(); ++i)
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{
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DspRomHashes& rom = KNOWN_ROMS[i];
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const DspRomHashes& rom = known_roms[i];
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if (hash_irom == rom.hash_irom && hash_drom == rom.hash_drom)
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rom_idx = i;
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rom_idx = static_cast<int>(i);
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}
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if (rom_idx < 0)
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@ -115,33 +121,20 @@ bool DSPCore_Init(const DSPInitOptions& opts)
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memset(&g_dsp.r,0,sizeof(g_dsp.r));
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for (int i = 0; i < 4; i++)
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{
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g_dsp.reg_stack_ptr[i] = 0;
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for (int j = 0; j < DSP_STACK_DEPTH; j++)
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{
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g_dsp.reg_stack[i][j] = 0;
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}
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}
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std::fill(std::begin(g_dsp.reg_stack_ptr), std::end(g_dsp.reg_stack_ptr), 0);
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for (size_t i = 0; i < ArraySize(g_dsp.reg_stack); i++)
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std::fill(std::begin(g_dsp.reg_stack[i]), std::end(g_dsp.reg_stack[i]), 0);
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// Fill IRAM with HALT opcodes.
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for (int i = 0; i < DSP_IRAM_SIZE; i++)
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{
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g_dsp.iram[i] = 0x0021; // HALT opcode
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}
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std::fill(g_dsp.iram, g_dsp.iram + DSP_IRAM_SIZE, 0x0021);
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// Just zero out DRAM.
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for (int i = 0; i < DSP_DRAM_SIZE; i++)
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{
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g_dsp.dram[i] = 0;
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}
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std::fill(g_dsp.dram, g_dsp.dram + DSP_DRAM_SIZE, 0);
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// Copied from a real console after the custom UCode has been loaded.
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// These are the indexing wrapping registers.
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g_dsp.r.wr[0] = 0xffff;
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g_dsp.r.wr[1] = 0xffff;
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g_dsp.r.wr[2] = 0xffff;
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g_dsp.r.wr[3] = 0xffff;
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std::fill(std::begin(g_dsp.r.wr), std::end(g_dsp.r.wr), 0xffff);
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g_dsp.r.sr |= SR_INT_ENABLE;
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g_dsp.r.sr |= SR_EXT_INT_ENABLE;
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@ -184,10 +177,7 @@ void DSPCore_Reset()
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{
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g_dsp.pc = DSP_RESET_VECTOR;
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g_dsp.r.wr[0] = 0xffff;
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g_dsp.r.wr[1] = 0xffff;
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g_dsp.r.wr[2] = 0xffff;
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g_dsp.r.wr[3] = 0xffff;
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std::fill(std::begin(g_dsp.r.wr), std::end(g_dsp.r.wr), 0xffff);
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DSPAnalyzer::Analyze();
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}
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@ -242,7 +242,7 @@ struct SDSP
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std::atomic<u32> mbox[2];
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// Accelerator / DMA / other hardware registers. Not GPRs.
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u16 ifx_regs[256];
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std::array<u16, 256> ifx_regs;
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// When state saving, all of the above can just be memcpy'd into the save state.
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// The below needs special handling.
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@ -21,10 +21,7 @@ static void gdsp_do_dma();
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void gdsp_ifx_init()
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{
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for (int i = 0; i < 256; i++)
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{
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g_dsp.ifx_regs[i] = 0;
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}
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g_dsp.ifx_regs.fill(0);
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g_dsp.mbox[0].store(0);
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g_dsp.mbox[1].store(0);
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@ -74,7 +74,7 @@ void DSPLLE::DoState(PointerWrap &p)
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}
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p.Do(g_dsp.step_counter);
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p.Do(g_dsp.ifx_regs);
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p.DoArray(g_dsp.ifx_regs);
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p.Do(g_dsp.mbox[0]);
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p.Do(g_dsp.mbox[1]);
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UnWriteProtectMemory(g_dsp.iram, DSP_IRAM_BYTE_SIZE, false);
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