Started cleaning up the ext_op code
Trying to get rid of the case and use a table like the main opcodes not sure how to handle epilog/prolog... maybe another table? git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2951 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nakeee
parent
c1fe6def46
commit
4fa154bb56
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@ -1752,8 +1752,7 @@ void msubx(const UDSPInstruction& opc)
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// MADDC $acS.m, $axT.h
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// 1110 10st xxxx xxxx
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// Multiply middle part of accumulator $acS.m by high part of secondary
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// accumulator $axT.h (treat them both as signed) and add result to product
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// register.
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// accumulator $axT.h (treat them both as signed) and add result to product register.
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void maddc(const UDSPInstruction& opc)
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{
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u32 sreg = (opc.hex >> 9) & 0x1;
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@ -1789,28 +1788,28 @@ void msubc(const UDSPInstruction& opc)
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Update_SR_Register64(prod);
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}
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// SRS @M, $(0x18+S)
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// SRS @M, $(DSP_REG_AXL0+S)
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// 0010 1sss mmmm mmmm
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// Store value from register $(0x18+S) to a memory pointed by address M.
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// Store value from register $(DSP_REG_AXL0+S) to a memory pointed by address M.
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// (8-bit sign extended).
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// FIXME: Perform additional operation depending on destination register.
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// Note: pc+=2 in duddie's doc seems wrong
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void srs(const UDSPInstruction& opc)
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{
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u8 reg = ((opc.hex >> 8) & 0x7) + 0x18;
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u8 reg = ((opc.hex >> 8) & 0x7) + DSP_REG_AXL0;
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u16 addr = (u16)(s16)(s8)opc.hex;
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dsp_dmem_write(addr, g_dsp.r[reg]);
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}
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// LRS $(0x18+D), @M
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// LRS $(DSP_REG_AXL0+D), @M
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// 0010 0ddd mmmm mmmm
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// Move value from data memory pointed by address M (8-bit sign
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// extended) to register $(0x18+D).
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// extended) to register $(DSP_REG_AXL0+D).
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// FIXME: Perform additional operation depending on destination register.
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// Note: pc+=2 in duddie's doc seems wrong
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void lrs(const UDSPInstruction& opc)
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{
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u8 reg = ((opc.hex >> 8) & 0x7) + 0x18;
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u8 reg = ((opc.hex >> 8) & 0x7) + DSP_REG_AXL0;
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u16 addr = (u16)(s16)(s8)opc.hex;
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g_dsp.r[reg] = dsp_dmem_read(addr);
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}
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@ -62,7 +62,6 @@ void nop(const UDSPInstruction& opc) {if(opc.hex) DSPInterpreter::unknown(opc);}
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// Zelda Four Swords: 02ca
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// TODO: Fill up the tables with the corresponding instructions
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DSPOPCTemplate opcodes[] =
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{
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{"NOP", 0x0000, 0xffff, nop, nop, 1, 0, {}, NULL, NULL},
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@ -306,30 +305,39 @@ DSPOPCTemplate opcodes[] =
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DSPOPCTemplate opcodes_ext[] =
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{
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{"L", 0x0040, 0x00c4, nop, nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LN", 0x0044, 0x00c4, nop, nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"DR", 0x0004, 0x00fc, DSPInterpreter::Ext::dr, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"IR", 0x0008, 0x00fc, DSPInterpreter::Ext::ir, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"NR", 0x000c, 0x00fc, DSPInterpreter::Ext::nr, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"MV", 0x0010, 0x00f0, DSPInterpreter::Ext::mv, nop, 1, 2, {{P_REG18, 1, 0, 2, 0x000c}, {P_REG1C, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"S", 0x0020, 0x00e4, DSPInterpreter::Ext::s, nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, NULL, NULL,},
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{"SN", 0x0024, 0x00e4, DSPInterpreter::Ext::sn, nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, NULL, NULL,},
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{"L", 0x0040, 0x00c4, DSPInterpreter::Ext::l, nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LN", 0x0044, 0x00c4, DSPInterpreter::Ext::ln, nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LS", 0x0080, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
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{"LSN", 0x0084, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
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{"LSM", 0x0088, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
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{"LSNM", 0x008c, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
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{"SL", 0x0082, 0x00ce, nop, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, NULL, NULL,},
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{"LSN", 0x0084, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
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{"SLN", 0x0086, 0x00ce, nop, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, NULL, NULL,},
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{"LSM", 0x0088, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
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{"SLM", 0x008a, 0x00ce, nop, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, NULL, NULL,},
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{"LSNM", 0x008c, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
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{"SLNM", 0x008e, 0x00ce, nop, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, NULL, NULL,},
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{"S", 0x0020, 0x00e4, nop, nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, NULL, NULL,},
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{"SN", 0x0024, 0x00e4, nop, nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, NULL, NULL,},
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{"LDX", 0x00c0, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},
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// FIXME what are the LDx? for?
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/* {"LDX", 0x00c0, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},
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{"LDXN", 0x00c4, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},
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{"LDXM", 0x00c8, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},
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{"LDXNM", 0x00cc, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},
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{"LD", 0x00c0, 0x00cc, nop, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LDN", 0x00c4, 0x00cc, nop, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LDM", 0x00c8, 0x00cc, nop, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LDNM", 0x00cc, 0x00cc, nop, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"MV", 0x0010, 0x00f0, nop, nop, 1, 2, {{P_REG18, 1, 0, 2, 0x000c}, {P_REG1C, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"DR", 0x0004, 0x00fc, nop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"IR", 0x0008, 0x00fc, nop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"NR", 0x000c, 0x00fc, nop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LDXNM", 0x00cc, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},*/
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{"LD", 0x00c0, 0x00cc, DSPInterpreter::Ext::ld, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LDN", 0x00c4, 0x00cc, DSPInterpreter::Ext::ldn, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LDM", 0x00c8, 0x00cc, DSPInterpreter::Ext::ldm, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"LDNM", 0x00cc, 0x00cc, DSPInterpreter::Ext::ldnm, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"XXX", 0x0000, 0x0000, nop, nop, 1, 1, {{P_VAL, 1, 0, 0, 0x00ff}}, NULL, NULL,},
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};
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@ -22,37 +22,190 @@
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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====================================================================*/
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//
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//
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// At the moment just ls and sl are using the prolog
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// perhaps all actions on r03 must be in the prolog
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//
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#include "Globals.h"
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#include "Globals.h"
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#include "gdsp_opcodes_helper.h"
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// Extended opcodes do not exist on their own. These opcodes can only be
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// attached to opcodes that allow extending (8 lower bits of opcode not used by
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// opcode). Extended opcodes do not modify program counter $pc register.
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namespace DSPInterpreter
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{
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namespace Ext
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{
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// DR $arR
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// xxxx xxxx 0000 01rr
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// Decrement addressing register $arR.
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void dr(const UDSPInstruction& opc) {
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u8 reg = opc.hex & 0x3;
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g_dsp.r[reg]--;
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}
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// IR $arR
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// xxxx xxxx 0000 10rr
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// Increment addressing register $arR.
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void ir(const UDSPInstruction& opc) {
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u8 reg = opc.hex & 0x3;
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g_dsp.r[reg]++;
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}
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// NR $arR
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// xxxx xxxx 0000 11rr
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// Add corresponding indexing register $ixR to addressing register $arR.
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void nr(const UDSPInstruction& opc) {
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u8 reg = opc.hex & 0x3;
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g_dsp.r[reg] += g_dsp.r[reg + DSP_REG_IX0];
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}
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// MV $axD, $acS.l
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// xxxx xxxx 0001 ddss
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// Move value of $acS.l to the $axD.l.
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void mv(const UDSPInstruction& opc)
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{
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u8 sreg = opc.hex & 0x3;
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u8 dreg = ((opc.hex >> 2) & 0x3);
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g_dsp.r[dreg + DSP_REG_AXL0] = g_dsp.r[sreg + DSP_REG_ACC0];
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}
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// S @$D, $acD.l
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// xxxx xxxx 001s s0dd
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// Store value of $(acS.l) in the memory pointed by register $D.
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// Post increment register $D.
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void s(const UDSPInstruction& opc)
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{
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u8 dreg = opc.hex & 0x3;
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u8 sreg = ((opc.hex >> 3) & 0x3) + DSP_REG_ACC0;
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dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
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g_dsp.r[dreg]++;
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}
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// SN @$D, $acD.l
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// xxxx xxxx 001s s1dd
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// Store value of register $acS in the memory pointed by register $D.
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// Add indexing register $ixD to register $D.
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void sn(const UDSPInstruction& opc)
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{
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u8 dreg = opc.hex & 0x3;
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u8 sreg = ((opc.hex >> 3) & 0x3) + DSP_REG_ACC0;
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dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
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g_dsp.r[dreg] += g_dsp.r[dreg + DSP_REG_IX0];
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}
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// L axD.l, @$S
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// xxxx xxxx 01dd d0ss
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// Load $axD with value from memory pointed by register $S.
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// Post increment register $S.
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void l(const UDSPInstruction& opc)
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{
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u8 sreg = opc.hex & 0x3;
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u8 dreg = ((opc.hex >> 3) & 0x7) + DSP_REG_AXL0;
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u16 val = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[dreg] = val;
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g_dsp.r[sreg]++;
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}
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// LN axD.l, @$S
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// xxxx xxxx 01dd d0ss
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// Load $axD with value from memory pointed by register $S.
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// Add indexing register register $ixS to register $S.
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void ln(const UDSPInstruction& opc)
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{
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u8 sreg = opc.hex & 0x3;
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u8 dreg = ((opc.hex >> 3) & 0x7) + DSP_REG_AXL0;
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u16 val = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[dreg] = val;
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g_dsp.r[sreg] += g_dsp.r[sreg + DSP_REG_IX0];
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}
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// Not in duddie's doc
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void ld(const UDSPInstruction& opc)
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{
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u8 dreg1 = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 dreg2 = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 sreg = opc.hex & 0x3;
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g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[dreg2] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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g_dsp.r[sreg]++;
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g_dsp.r[DSP_REG_AR3]++;
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}
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// Not in duddie's doc
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void ldn(const UDSPInstruction& opc)
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{
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u8 dreg1 = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 dreg2 = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 sreg = opc.hex & 0x3;
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g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[dreg2] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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g_dsp.r[sreg] += g_dsp.r[sreg + DSP_REG_IX0];
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g_dsp.r[DSP_REG_AR3]++;
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}
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// Not in duddie's doc
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void ldm(const UDSPInstruction& opc)
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{
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u8 dreg1 = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 dreg2 = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 sreg = opc.hex & 0x3;
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g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[dreg2] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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g_dsp.r[sreg]++;
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g_dsp.r[DSP_REG_AR3] += g_dsp.r[DSP_REG_IX3];
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}
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// Not in duddie's doc
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void ldnm(const UDSPInstruction& opc)
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{
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u8 dreg1 = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 dreg2 = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 sreg = opc.hex & 0x3;
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g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[dreg2] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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g_dsp.r[sreg] += g_dsp.r[sreg + DSP_REG_IX0];
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g_dsp.r[DSP_REG_AR3] += g_dsp.r[DSP_REG_IX3];
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}
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} // end namespace ext
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} // end namespace DSPInterpeter
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//
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void dsp_op_ext_r_epi(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 op = (opc.hex >> 2) & 0x3;
|
||||
u8 reg = opc.hex & 0x3;
|
||||
|
||||
switch (op)
|
||||
{
|
||||
case 0x00:
|
||||
switch (op) {
|
||||
case 0x00: //
|
||||
ERROR_LOG(DSPLLE, "dsp_op_ext_r_epi");
|
||||
break;
|
||||
|
||||
case 0x01:
|
||||
case 0x01: // DR
|
||||
g_dsp.r[reg]--;
|
||||
break;
|
||||
|
||||
case 0x02:
|
||||
case 0x02: // IR
|
||||
g_dsp.r[reg]++;
|
||||
break;
|
||||
|
||||
case 0x03:
|
||||
case 0x03: // NR
|
||||
g_dsp.r[reg] += g_dsp.r[reg + 4];
|
||||
break;
|
||||
}
|
||||
|
|
@ -75,13 +228,13 @@ void dsp_op_ext_s(const UDSPInstruction& opc)
|
|||
|
||||
dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
|
||||
|
||||
if (opc.hex & 0x04)
|
||||
if (opc.hex & 0x04) // SN
|
||||
{
|
||||
g_dsp.r[dreg] += g_dsp.r[dreg + 4];
|
||||
}
|
||||
else
|
||||
{
|
||||
g_dsp.r[dreg]++;
|
||||
g_dsp.r[dreg]++; // S
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -94,13 +247,13 @@ void dsp_op_ext_l(const UDSPInstruction& opc)
|
|||
u16 val = dsp_dmem_read(g_dsp.r[sreg]);
|
||||
g_dsp.r[dreg] = val;
|
||||
|
||||
if (opc.hex & 0x04)
|
||||
if (opc.hex & 0x04) // LN/LSMN
|
||||
{
|
||||
g_dsp.r[sreg] += g_dsp.r[sreg + 4];
|
||||
}
|
||||
else
|
||||
{
|
||||
g_dsp.r[sreg]++;
|
||||
g_dsp.r[sreg]++; // LS
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -110,11 +263,11 @@ void dsp_op_ext_ls_pro(const UDSPInstruction& opc)
|
|||
u8 areg = (opc.hex & 0x1) + 0x1e;
|
||||
dsp_dmem_write(g_dsp.r[0x03], g_dsp.r[areg]);
|
||||
|
||||
if (opc.hex & 0x8)
|
||||
if (opc.hex & 0x8) // LSM/LSMN
|
||||
{
|
||||
g_dsp.r[0x03] += g_dsp.r[0x07];
|
||||
}
|
||||
else
|
||||
else // LS
|
||||
{
|
||||
g_dsp.r[0x03]++;
|
||||
}
|
||||
|
|
@ -127,11 +280,11 @@ void dsp_op_ext_ls_epi(const UDSPInstruction& opc)
|
|||
u16 val = dsp_dmem_read(g_dsp.r[0x00]);
|
||||
dsp_op_write_reg(dreg, val);
|
||||
|
||||
if (opc.hex & 0x4)
|
||||
if (opc.hex & 0x4) // LSN/LSMN
|
||||
{
|
||||
g_dsp.r[0x00] += g_dsp.r[0x04];
|
||||
}
|
||||
else
|
||||
else // LS
|
||||
{
|
||||
g_dsp.r[0x00]++;
|
||||
}
|
||||
|
|
@ -143,11 +296,11 @@ void dsp_op_ext_sl_pro(const UDSPInstruction& opc)
|
|||
u8 areg = (opc.hex & 0x1) + 0x1e;
|
||||
dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
|
||||
|
||||
if (opc.hex & 0x4)
|
||||
if (opc.hex & 0x4) // SLN/SLNM
|
||||
{
|
||||
g_dsp.r[0x00] += g_dsp.r[0x04];
|
||||
}
|
||||
else
|
||||
else // SL
|
||||
{
|
||||
g_dsp.r[0x00]++;
|
||||
}
|
||||
|
|
@ -160,11 +313,11 @@ void dsp_op_ext_sl_epi(const UDSPInstruction& opc)
|
|||
u16 val = dsp_dmem_read(g_dsp.r[0x03]);
|
||||
dsp_op_write_reg(dreg, val);
|
||||
|
||||
if (opc.hex & 0x8)
|
||||
if (opc.hex & 0x8) // SLM/SLMN
|
||||
{
|
||||
g_dsp.r[0x03] += g_dsp.r[0x07];
|
||||
}
|
||||
else
|
||||
else // SL
|
||||
{
|
||||
g_dsp.r[0x03]++;
|
||||
}
|
||||
|
|
@ -179,7 +332,7 @@ void dsp_op_ext_ld(const UDSPInstruction& opc)
|
|||
g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[sreg]);
|
||||
g_dsp.r[dreg2] = dsp_dmem_read(g_dsp.r[0x03]);
|
||||
|
||||
if (opc.hex & 0x04)
|
||||
if (opc.hex & 0x04) // N
|
||||
{
|
||||
g_dsp.r[sreg] += g_dsp.r[sreg + 0x04];
|
||||
}
|
||||
|
|
@ -188,7 +341,7 @@ void dsp_op_ext_ld(const UDSPInstruction& opc)
|
|||
g_dsp.r[sreg]++;
|
||||
}
|
||||
|
||||
if (opc.hex & 0x08)
|
||||
if (opc.hex & 0x08) // M
|
||||
{
|
||||
g_dsp.r[0x03] += g_dsp.r[0x07];
|
||||
}
|
||||
|
|
@ -276,6 +429,7 @@ void dsp_op_ext_ops_epi(const UDSPInstruction& opc)
|
|||
{
|
||||
dsp_op_ext_ls_epi(opc.hex);
|
||||
}
|
||||
break;
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -37,5 +37,37 @@
|
|||
void dsp_op_ext_ops_pro(const UDSPInstruction& opc); // run any prologs
|
||||
void dsp_op_ext_ops_epi(const UDSPInstruction& opc); // run any epilogs
|
||||
|
||||
namespace DSPInterpreter
|
||||
{
|
||||
namespace Ext
|
||||
{
|
||||
|
||||
void l(const UDSPInstruction& opc);
|
||||
void ln(const UDSPInstruction& opc);
|
||||
void ls(const UDSPInstruction& opc);
|
||||
void lsn(const UDSPInstruction& opc);
|
||||
void lsm(const UDSPInstruction& opc);
|
||||
void lsnm(const UDSPInstruction& opc);
|
||||
void sl(const UDSPInstruction& opc);
|
||||
void sln(const UDSPInstruction& opc);
|
||||
void slm(const UDSPInstruction& opc);
|
||||
void slnm(const UDSPInstruction& opc);
|
||||
void s(const UDSPInstruction& opc);
|
||||
void sn(const UDSPInstruction& opc);
|
||||
void ldx(const UDSPInstruction& opc);
|
||||
void ldxn(const UDSPInstruction& opc);
|
||||
void ldxm(const UDSPInstruction& opc);
|
||||
void ldxnm(const UDSPInstruction& opc);
|
||||
void ld(const UDSPInstruction& opc);
|
||||
void ldn(const UDSPInstruction& opc);
|
||||
void ldm(const UDSPInstruction& opc);
|
||||
void ldnm(const UDSPInstruction& opc);
|
||||
void mv(const UDSPInstruction& opc);
|
||||
void dr(const UDSPInstruction& opc);
|
||||
void ir(const UDSPInstruction& opc);
|
||||
void nr(const UDSPInstruction& opc);
|
||||
|
||||
} // end namespace Ext
|
||||
} // end namespace DSPinterpeter
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue